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公开(公告)号：KR101367988B1
公开(公告)日：2014-02-28
申请号：KR1020120142808
申请日：2012-12-10
Applicant: 한국과학기술원
IPC: H01L21/336 , H01L29/78
CPC classification number: H01L29/66795 , H01L29/785
Abstract: The purpose of the present invention is to provide a transistor having improved performance than a conventional FinFET by manufacturing a UTFinFET having an ultra-thin fin (UTFin) whose thickness is thinner than that of a fin which can be manufactured by a conventional FinFET manufacturing process. In order to achieve the purpose, a semiconductor device according to the present invention comprises a step of forming two Si-UTFins which protrude from a substrate and are formed on both sides of a fin made of Si and SiGe layers using an epitaxy method. The UTFin formed in this method replaces the role of a fin of a conventional FinFET. A UTFin formed using an epitaxy method overcomes a thickness limit which a fin formed by lithography has, and can have a thickness of less than 10 nm. [Reference numerals] (AA) Step of preparing a Si substrate; (BB) Step of forming a SiGe layer; (CC) Step of placing a hard mask on a Si-Fin area by patterning the hard mask on the SiGe layer; (DD) Step of forming a Si-Fin through an etching process; (EE) Step of growing a Si layer on both sides of the Si-Fin and both sides of the SiGe layer in an epitaxy method; (FF) Step of forming a first impurity doped resign by firstly doping an impurity into a Si-UTFin; (GG) Step of etching the hard mask; (HH) Step of firstly depositing oxide in a region etched while forming the Si-Fin, making an oxide surface even, and etching the oxide; (II) Step of forming two Si-UTFins on both sides of the Si-Fin and both sides of the SiGe layer; (JJ) Step of forming an intermediate dielectric layer by filling dielectric material between two Si-UTFins; (KK) Step of leaving the intermediate dielectric layer between two Si-UTFins and removing the intermediate dielectric layer on outer walls of two Si-UTFins through an etching process; (LL) Step of secondly depositing oxide on the outer walls of two Si-UTFins and the intermediate dielectric layer and making an oxide surface even; (MM) Step of depositing a gate stack electrode; (NN) Step of forming source and drain regions which are second and third impurity regions respectively by secondly and thirdly doping on left and right sides of the Si-UTFin
Abstract translation: 本发明的目的是通过制造具有厚度比通过常规FinFET制造工艺制造的鳍片厚度的超薄鳍片（UTFin）的UTFinFET来提供具有比常规FinFET具有改进的性能的晶体管 。 为了实现这一目的，本发明的半导体器件包括从基板突出并且使用外延法在由Si和SiGe层制成的鳍的两侧上形成两个Si-UTFin的步骤。 以该方法形成的UTFin替代了常规FinFET鳍片的作用。 使用外延法形成的UTFin克服了通过光刻形成的翅片的厚度限制，并且可以具有小于10nm的厚度。 （附图标记）（AA）制备Si衬底的步骤; （BB）形成SiGe层的步骤; （CC）通过在SiGe层上构图硬掩模，将硬掩模放置在Si-Fin区域上的步骤; （DD）通过蚀刻工艺形成Si-Fin的步骤; （EE）在外延法中在Si-Fin两面和SiGe层的两面上生长Si层的步骤; （FF）通过首先将杂质掺杂到Si-UTFin中形成第一杂质掺杂的步骤; （GG）蚀刻硬掩模的步骤; （HH）在形成Si-Fin的同时蚀刻的区域中首先沉积氧化物，使氧化物表面均匀并蚀刻氧化物的步骤; （II）在Si-Fin两面和SiGe层的两侧形成两个Si-UTFin的步骤; （JJ）通过在两个Si-UTF之间填充介电材料形成中间介电层的步骤; （KK）通过蚀刻工艺在两个Si-UTFins之间离开中间介电层并去除两个Si-UTFin的外壁上的中间介电层; （LL）在两个Si-UTFin和中间介电层的外壁上二次沉积氧化物并使氧化物表面均匀的步骤; （MM）沉积栅堆叠电极的步骤; （NN）通过在Si-UTFin的左侧和右侧二次和三次掺杂而分别形成第二和第三杂质区的源区和漏区的步骤
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公开(公告)号：KR1020160089141A
公开(公告)日：2016-07-27
申请号：KR1020150008700
申请日：2015-01-19
Applicant: 한국과학기술원
IPC: H01L21/8226 , H03K3/59 , H01L27/02
CPC classification number: H03K19/16 , B82Y25/00 , G11C11/16 , H01L29/66984 , H01L43/02 , H01L43/08 , H01L43/10 , H03B15/006 , H03K19/018578 , H01L21/8226 , H01L27/0218 , H03K3/59
Abstract: 네거티브커패시턴스로직디바이스는제1 전계효과트랜지스터(field effect transistor, 이하 FET) 및제2 FET를포함한다. 상기제1 FET는전원전압과출력노드사이에연결되고, 네거티브커패시턴스를강유전체를구비한다. 상기제2 FET는상기출력노드와접지전압사이에연결되고, 네거티브커패시턴스를갖는강유전체를구비한다. 상기네거티브커패시턴스로직디바이스는입력노드에인가되는입력전압을미분하여상기출력노드로출력전압을제공한다.
Abstract translation: 负电容逻辑器件包括第一场效应晶体管（FET）和第二FET。 第一FET连接在电源电压和输出节点之间，并且包括具有负电容的铁电物质。 第二FET连接在输出节点和接地电压之间，并且包括具有负电容的铁电物质。 负电容逻辑器件区分施加到输入节点的输入电压并向输出节点提供输出电压。 因此，负电容逻辑器件可以减少占用面积。
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3.发明授权독립적으로 구동이 가능하고 다른 일함수를 가지는 이중 게이트 구조를 포함하는 전자-정공 이중층 터널 전계 효과 트랜지스터 및 그 제조 방법 有权独立和不同工作功能双门控电子孔双层隧道场效应晶体管及其制造方法
公开(公告)号：KR101424755B1
公开(公告)日：2014-07-31
申请号：KR1020130000433
申请日：2013-01-03
Applicant: 한국과학기술원
IPC: H01L29/78 , H01L21/336
Abstract: 본 발명은 대칭적인 PMOS 및 NMOS 이중 게이트 구조를 가지는 전자-정공 이중층 터널 전계효과 트랜지스터 및 상기 트랜지스터의 제조방법에 관한 것으로, 이중 게이트 pin구조 및 밴드간 터널링을 이용한 것으로서 문턱전압 이하에서의 기울기의 개선과 동작 전류의 증가를 가져올 수 있고, 대칭구조의 게이트를 제안함으로써 실제 구현가능한 대칭적인 이중 게이트 구조를 가지는 임계 전압(threshold voltage)이 작아져 공급 전력을 줄일 수 있다는 장점이 있는 전자-정공 이중층 터널 전계효과 트랜지스터 및 상기 트랜지스터의 제조방법에 관한 것이다.
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公开(公告)号：KR101402697B1
公开(公告)日：2014-06-03
申请号：KR1020120143844
申请日：2012-12-11
Applicant: 한국과학기술원
IPC: H01L21/336 , H01L29/78
CPC classification number: H01L29/7855 , H01L29/66931
Abstract: The present invention relates to an electron-hole bilayer tunnel field effect transistor using a symmetrical double gate structure and a manufacturing method of the transistor and, more specifically, to an electron-hole bilayer tunnel field effect transistor using a symmetrical double gate structure and a manufacturing method of the transistor, capable of bringing the improvement of a slope and an increase in an operation current under a threshold voltage by using a double gate p-i-n structure and inter-band tunneling; and being formed in practice by suggesting the symmetrical gate structure.
Abstract translation: 本发明涉及使用对称双栅极结构的电子 - 空穴双层隧道场效应晶体管及其制造方法，更具体地说，涉及使用对称双栅结构的电子 - 空穴双层隧道场效应晶体管和 晶体管的制造方法，能够通过使用双栅极引脚结构和带间隧穿来提高斜率的提高和阈值电压下的工作电流的增加; 并且通过提出对称的门结构在实践中形成。
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公开(公告)号：KR101438797B1
公开(公告)日：2014-09-16
申请号：KR1020130015754
申请日：2013-02-14
Applicant: 한국과학기술원
Abstract: 본원 발명은 수직 나노구조를 이용하여 광학 기기 등을 제작하는 방법으로, Si, Ge 등의 단결정 반도체 기판, GaAs, InP 등의 III-V 화합물 반도체 기판, SOI (silicon on insulator) 기판 중 적어도 어느 하나인 기판을 준비 단계, 상기 세정된 기판 상에 리소그라피(Lithography) 방법, 셀프 어셈블리 템플릿(Self-assembly template) 방법 중 어느 하나 이상의 방법을 이용하여 원하는 수직 나노 구조를 패터닝 하는 단계, 금, 은, 백금 등의 금속 중 어느 하나, 둘 이상의 조합을 포함하는 촉매 금속을 최종적으로 완성하고자 하는 수직 나노구조의 역상 패턴으로 기판 상부에 증착하는 단계, 불산(HF)과 과산화수소(H
2 O
2 ) 혼합 수용액에 담지하는 금속 촉매 식각 방법을 이용하여 수직 나노구조를 제작하는 단계 등을 이용한다.
이를 통해, 금속 촉매 식각 방법을 이용하여 격자 구조를 제작함으로써, 보다 더 미세하고, 정교한 패턴들을 용이하게 제작하고자 한다.
이와 같이 제작된 SWG 구조를 가진 나노 구조를 갖는 광학 기기는 기존의 건식 식각을 이용하여 제작된 구조에 비하여 보다 더 효과적인 성능을 가질 수 있다.-
Patent Agency Ranking6.发明公开독립적으로 구동이 가능하고 다른 일함수를 가지는 이중 게이트 구조를 포함하는 전자-정공 이중층 터널 전계 효과 트랜지스터 및 그 제조 방법 有权独立和不同的工作原理双电位孔双层隧道场效应晶体管及其制造方法
公开(公告)号：KR1020140088658A
公开(公告)日：2014-07-11
申请号：KR1020130000433
申请日：2013-01-03
Applicant: 한국과학기술원
IPC: H01L29/78 , H01L21/336
CPC classification number: H01L21/823821 , H01L29/66795 , H01L29/7855
Abstract: The present invention relates to an electron-hole bilayer tunnel field effect transistor having a symmetric PMOS and NMOS double gate structure and a fabrication method for the same. The electron-hole bilayer tunnel field effect transistor increases an operation current and a gradient under a threshold voltage by using a double gate p-i-n structure and tunneling between bands and reduces supply power by decreasing the threshold voltage which has a symmetric double gate structure which can be realized by a gate of a symmetric structure.
Abstract translation: 本发明涉及具有对称PMOS和NMOS双栅极结构的电子 - 空穴双层隧道场效应晶体管及其制造方法。 电子 - 空穴双层隧道场效应晶体管通过使用双栅极引脚结构和带间隧穿，增加阈值电压下的工作电流和梯度，并通过降低具有对称双栅极结构的阈值电压来降低电源功率，该阈值电压可以是 由对称结构的门实现。
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公开(公告)号：KR101880192B1
公开(公告)日：2018-07-20
申请号：KR1020170046768
申请日：2017-04-11
Applicant: 한국과학기술원
IPC: G06F17/50
CPC classification number: G06F17/5036 , G06F2217/78 , G06F17/5009
Abstract: 반도체소자의특성시뮬레이션방법은밀도함수이론(density functional theory; DFT)을이용하여대상반도체소자의원자간상호작용에너지정보를나타내는해밀토니언(Hamiltonian) 및중첩매트릭스를추출하고, 유효에너지영역에내에서의해밀토니언및 중첩매트릭스와에너지-k 관계식에기초하여해당에너지각각에대한블로흐스테이트(Bloch state)들을각각산출하며, 블로흐스테이트들을표현하는매트릭스를직교화(orthonormalization)한변환매트릭스에해밀토니언및 중첩매트릭스를적용하여매트릭스사이즈가줄어든제1 축소해밀토니언및 제1 축소중첩매트릭스를얻는다. 또한, 해밀토니언및 중첩매트릭스에기초하여산출된제1 에너지밴드구조와제1 축소해밀토니언및 제1 축소중첩매트릭스에기초하여산출된제2 에너지밴드구조를비교하여유효에너지영역내에서제2 에너지밴드구조에서제1 에너지밴드구조와대응하지않는에너지밴드인비물리적가지들(unphysical branch)이모두제거된최종변환매트릭스및 최종에너지밴드구조를산출한다.
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公开(公告)号：KR1020140102451A
公开(公告)日：2014-08-22
申请号：KR1020130015754
申请日：2013-02-14
Applicant: 한국과학기술원
CPC classification number: G02B6/0229 , B82Y40/00 , G02B2207/101 , G03F1/14 , H01L29/0665 , H01L29/0692
Abstract: The present invention relates to a manufacturing method for an optical apparatus, etc. using a vertical nanostructure, which comprises: a step of preparing at least one substrate among a single crystal semiconductor substrate such as Si and Ge, a III-V compound semiconductor substrate such as GaAs and InP, and a silicon on insulator (SOI); a step of patterning a desired vertical nanostructure on the washed substrate using one or more methods between a lithography method and a self-assembly template method; a step of depositing catalyst metal, which includes one among gold, silver, platinum, and two or more combinations thereof, on the upper part of the substrate in a reverse pattern of the vertical nanostructure to be finally completed; and a step of manufacturing the vertical nanostructure using a metal catalyst etching method which is to submerge into a solution where hydrofluoric acid (HF) and hydrogen peroxide (H_2O_2) are mixed. Therefore, the manufacturing method can easily manufacture fine and elaborate patterns by manufacturing a grid structure using the metal catalyst etching method. The optical apparatus with a SWG nanostructure manufactured thereby can provide more effective performance than a structure manufactured by an existing dry etching method.
Abstract translation: 本发明涉及使用垂直纳米结构的光学装置等的制造方法，其包括：在诸如Si和Ge的单晶半导体衬底中制备至少一个衬底的步骤，III-V族化合物半导体衬底 例如GaAs和InP，以及绝缘体上硅（SOI）; 在光刻方法和自组装模板方法之间使用一种或多种方法在洗涤的衬底上图案化所需的垂直纳米结构的步骤; 在垂直纳米结构的反向图案中，在基板的上部沉积包含金，银，铂及其两种或更多种组合的催化剂金属的步骤，以最终完成; 以及使用浸渍在氢氟酸（HF）和过氧化氢（H_2O_2））的溶液中的金属催化剂蚀刻法制造立式纳米结构体的工序。 因此，通过使用金属催化剂蚀刻方法制造栅格结构，可以容易地制造精细和精细的图案。 由此制造的具有SWG纳米结构的光学装置可以比通过现有的干蚀刻方法制造的结构提供更有效的性能。
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9.发明授权수직 구조를 갖는 독립적 및 대칭적인 이중 게이트 구조를 이용한 전자-정공 이중층 터널 전계 효과 트랜지스터 및 그 제조 방법 有权具有独立和对称双门的垂直结构化电子双层隧道场效应晶体管的建议和制造方法
公开(公告)号：KR101368191B1
公开(公告)日：2014-02-28
申请号：KR1020130000434
申请日：2013-01-03
Applicant: 한국과학기술원
IPC: H01L21/336 , H01L29/78
CPC classification number: H01L29/66666 , H01L29/66931 , H01L29/7827
Abstract: The present invention relates to an electronic-hole double layer tunnel field effect transistor, where a source region, a channel and a drain region are arranged at a substrate in a vertical direction, including a double gate structure. The present invention relates to the electronic-hole double layer tunnel field effect transistor and a manufacturing method thereof capable of increasing the degree of integration of the transistor at the substrate by having a vertical structure, being the electronic-hole double layer tunnel field effect transistor by applying different electrodes to the double gate structure, improving the inclination under threshold voltage and increasing operating current by using a double gate p-i-n structure and tunneling between bands, and having an implementable symmetrical double gate structure by proposing a gate of a symmetrical structure.
Abstract translation: 本发明涉及一种电子双层隧道场效应晶体管，其中源极区，沟道和漏极区在垂直方向的衬底上排列，包括双栅结构。 电子双层隧道场效应晶体管及其制造方法技术领域本发明涉及电子双层隧道场效应晶体管及其制造方法，该晶体管的制造方法能够通过具有垂直结构来提高晶体管在基板上的集成度，作为电子双层隧道场效应晶体管 通过对双栅极结构施加不同的电极，通过使用双栅极引脚结构和带之间的隧穿，提高阈值电压下的倾斜度和提高工作电流，并且通过提出对称结构的栅极具有可实现的对称双栅极结构。
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公开(公告)号：KR101367989B1
公开(公告)日：2014-02-28
申请号：KR1020120143638
申请日：2012-12-11
Applicant: 한국과학기술원
IPC: H01L21/336 , H01L29/78
CPC classification number: H01L29/66795 , H01L29/785
Abstract: The purpose of the present invention is to provide a transistor having improved performance than a conventional FinFET by manufacturing a UTFinFET having an ultra-thin fin (UTFin) whose thickness is thinner than that of a fin which can be manufactured by a conventional FinFET manufacturing process. In order to achieve the purpose, a semiconductor device according to the present invention comprises a step of forming two Si-UTFins which protrude from a substrate and are formed on both sides of a fin made of Si and SiGe layers using an epitaxy method. The UTFin formed in this method replaces the role of a fin of a conventional FinFET. A UTFin formed using an epitaxy method overcomes a thickness limit which a fin formed by lithography has, and can have a thickness of less than 10 nm. [Reference numerals] (AA) Step of preparing a Si substrate; (BB) Step of forming a SiGe layer; (CC) Step of placing a hard mask on a Si-Fin area by patterning the hard mask on the SiGe layer; (DD) Step of forming a Si-Fin through an etching process; (EE) Step of growing a Si layer on both sides of the Si-Fin and both sides of the SiGe layer in an epitaxy method; (FF) Step of forming a first impurity resign by firstly doping an impurity into a Si-UTFin; (GG) Step of etching the hard mask; (HH) Step of firstly depositing oxide in a region etched while forming the Si-Fin, making an oxide surface even, and etching the oxide; (II) Step of forming two Si-UTFins on both sides of the Si-Fin and both sides of the SiGe layer; (JJ) Step of forming an air filled structure in a space formed by a secondly deposited oxide, the lower part of the Si-UTFin, and the Si-Fin by secondly depositing oxide onto inner walls, outer walls, top between two Si-UTFins under poor step coverage conditions and making an oxide surface even; (KK) Step of depositing a gate stack electrode; (LL) Step of forming source and drain regions which are second and third impurity regions respectively by secondly and thirdly doping on left and right sides of the Si-UTFin
Abstract translation: 本发明的目的是通过制造具有厚度比通过常规FinFET制造工艺制造的鳍片厚度的超薄鳍片（UTFin）的UTFinFET来提供具有比常规FinFET具有改进的性能的晶体管 。 为了实现这一目的，本发明的半导体器件包括从基板突出并且使用外延法在由Si和SiGe层制成的鳍的两侧上形成两个Si-UTFin的步骤。 以该方法形成的UTFin替代了常规FinFET鳍片的作用。 使用外延法形成的UTFin克服了通过光刻形成的翅片的厚度限制，并且可以具有小于10nm的厚度。 （附图标记）（AA）制备Si衬底的步骤; （BB）形成SiGe层的工序; （CC）通过在SiGe层上构图硬掩模，将硬掩模放置在Si-Fin区域上的步骤; （DD）通过蚀刻工艺形成Si-Fin的步骤; （EE）在外延法中在Si-Fin两面和SiGe层的两面上生长Si层的步骤; （FF）通过首先将杂质掺杂到Si-UTFin中来形成第一杂质的步骤; （GG）蚀刻硬掩模的步骤; （HH）在形成Si-Fin的同时蚀刻的区域中首先沉积氧化物，使氧化物表面均匀并蚀刻氧化物的步骤; （II）在Si-Fin两面和SiGe层的两侧形成两个Si-UTFin的步骤; （JJ）在由二次沉积的氧化物形成的空间中形成充气结构的步骤，Si-UTFin的下部和通过将氧化物二次沉积到内壁，外壁，两个Si- UTFins在较差的步骤覆盖条件下，使氧化物表面均匀; （KK）沉积栅堆叠电极的步骤; （LL）通过在Si-UTFin的左侧和右侧二次和三次掺杂而分别形成第二和第三杂质区的源区和漏区的步骤
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