ONE TERMINAL CAPACITOR INTERFACE CIRCUIT
    3.
    发明申请
    ONE TERMINAL CAPACITOR INTERFACE CIRCUIT 审中-公开
    一个终端电容接口电路

    公开(公告)号:WO2006098976A3

    公开(公告)日:2007-04-05

    申请号:PCT/US2006008214

    申请日:2006-03-08

    CPC classification number: G01D5/24 G01P15/125 H03M3/34 H03M3/458

    Abstract: A one terminal capacitor interface circuit (40) for sensing the capacitance of a capacitor (52) includes a differential integrating amplifier (44) having an input common mode voltage and two summing nodes (66) and (68) whose voltage is substantially equal to the input common mode voltage, a switching circuit (57) for charging the capacitor (52) to a first voltage level (Vx) in a first phase(Phl ), connecting, in a second phase (Ph2), the capacitor (52) to one of the summing nodes (66) of the differential amplifier (44) to provide a first output (Vop); charging the capacitor (52) to a second voltage level (Vz) in a third phase (Ph3), and connecting, in a fourth phase (Ph4), the capacitor (52) to the other summing node (68) of the differential amplifier (44) to provide a second output (Von); the combined first and second outputs (Vop) and (Von), representing the capacitance of the capacitor (52) substantially independent of the input common mode voltage.

    Abstract translation: 用于感测电容器(52)的电容的单端电容器接口电路(40)包括具有输入共模电压的差分积分放大器(44)和两个加法节点(66)和(68),其电压基本上等于 所述输入共模电压,用于将所述电容器(52)充电到第一相(Ph1)中的第一电压电平(Vx)的开关电路(57),在第二相(Ph2)中连接所述电容器(52) 到差分放大器(44)的求和节点(66)之一以提供第一输出(Vop); 在第三相(Ph3)中将电容器(52)充电到第二电压电平(Vz),并且在第四相(Ph4)中将电容器(52)连接到差分放大器的另一个求和节点(68) (44)以提供第二输出(Von); 组合的第一和第二输出(Vop)和(Von),表示电容器(52)的电容基本上与输入共模电压无关。

    VARIABLE CAPACITANCE SWITCHED CAPACITOR INPUT SYSTEM AND METHOD
    6.
    发明公开
    VARIABLE CAPACITANCE SWITCHED CAPACITOR INPUT SYSTEM AND METHOD 有权
    与可变容量和程序开关电容输入系统

    公开(公告)号:EP1784916A4

    公开(公告)日:2007-11-14

    申请号:EP05761191

    申请日:2005-06-13

    CPC classification number: H03M3/34 H03M3/43

    Abstract: A variable capacitance switched capacitor input system and method includes a differential integrator circuit having first and second input summing nodes and a variable sensing capacitor; one terminal of the variable sensing capacitor is connected to one of the nodes in the first phase and to the other of the nodes in the second phase; an input terminal connected to a second terminal of the variable sensing capacitor receives a first voltage level in the first phase and a second voltage level in the second phase for delivering the charge on the variable sensing capacitor to the first summing node in the first phase and to the second summing node in the second phase and canceling errors in a differential integrator circuit output caused by leakage current.

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