公开(公告)号：DE69021712D1

公开(公告)日：1995-09-21

申请号：DE69021712

申请日：1990-02-08

Applicant: IBM

Inventor： ALAIWAN HAISSAM ,  BASSO CLAUDE ,  CALVIGNAC JEAN ,  COMBES JACQUES ,  KERMAREC FRANCOIS ,  PAUPORTE ANDRE

IPC: G06F11/14 ,  G06F11/20 ,  G06F15/16

Abstract: A checkpointing mechanism implemented in a data processing system comprising a dual processor configuration gives the system a fault tolerance capability while minimizing the complexity of both the software and the hardware. The active and backup processors are coupled asynchronously with some hardware assist functions comprising a memory change detector which captures the memory changes in the memory of the active processor and a mirroring control circuit which causes the memory changes when committed by establish recovery point signals generated by the active processor to be dumped into the memory of the back up processor so that the backup processor can resume the operations of the active processor from the last established recovery point. The active and backup processors may each be connected to a dedicated memory and recovery point storing means, or to a memory including two dual sides shared by all the processors for storing data structures and recovery points.

公开(公告)号：DE69029084D1

公开(公告)日：1996-12-12

申请号：DE69029084

申请日：1990-02-27

Applicant: IBM

Inventor： ALAIWAN HAISSAM

IPC: G06F9/46 ,  G06F9/54 ,  G06F15/167 ,  G06F11/20

Abstract: In the environment of a plurality of processors (9) interconnected by a shared intelligent memory (3), a mechanism for the secure passing of messages between tasks operated on said processors is provided. For inter-task message passing, means (13) are provided within the shared intelligent memory for storing the messages transmitted by sending tasks, and further, each processor includes serving means for getting the messages to be sent to the task operated by said each processor. The passing of messages from a processor to the shared intelligent memory and from the latter to another processor is made, using a set of high-level microcoded commands. Further, a process is provided, using the above cited message passing mechanism together with redundancies built into the shared memory, to ensure a fault-tolerant message passing, wherein the tasks operated primarily on a processor, are automatically replaced by back-up tasks executed on another processor if the first processor comes to fail.

公开(公告)号：DE69021712T2

公开(公告)日：1996-04-18

申请号：DE69021712

申请日：1990-02-08

Applicant: IBM

Inventor： ALAIWAN HAISSAM ,  BASSO CLAUDE ,  CALVIGNAC JEAN ,  COMBES JACQUES ,  KERMAREC FRANCOIS ,  PAUPORTE ANDRE

IPC: G06F11/14 ,  G06F11/20 ,  G06F15/16

Abstract: A checkpointing mechanism implemented in a data processing system comprising a dual processor configuration gives the system a fault tolerance capability while minimizing the complexity of both the software and the hardware. The active and backup processors are coupled asynchronously with some hardware assist functions comprising a memory change detector which captures the memory changes in the memory of the active processor and a mirroring control circuit which causes the memory changes when committed by establish recovery point signals generated by the active processor to be dumped into the memory of the back up processor so that the backup processor can resume the operations of the active processor from the last established recovery point. The active and backup processors may each be connected to a dedicated memory and recovery point storing means, or to a memory including two dual sides shared by all the processors for storing data structures and recovery points.