公开(公告)号：DE69021712T2

公开(公告)日：1996-04-18

申请号：DE69021712

申请日：1990-02-08

Applicant: IBM

Inventor： ALAIWAN HAISSAM ,  BASSO CLAUDE ,  CALVIGNAC JEAN ,  COMBES JACQUES ,  KERMAREC FRANCOIS ,  PAUPORTE ANDRE

IPC: G06F11/14 ,  G06F11/20 ,  G06F15/16

Abstract: A checkpointing mechanism implemented in a data processing system comprising a dual processor configuration gives the system a fault tolerance capability while minimizing the complexity of both the software and the hardware. The active and backup processors are coupled asynchronously with some hardware assist functions comprising a memory change detector which captures the memory changes in the memory of the active processor and a mirroring control circuit which causes the memory changes when committed by establish recovery point signals generated by the active processor to be dumped into the memory of the back up processor so that the backup processor can resume the operations of the active processor from the last established recovery point. The active and backup processors may each be connected to a dedicated memory and recovery point storing means, or to a memory including two dual sides shared by all the processors for storing data structures and recovery points.

公开(公告)号：DE69021712D1

公开(公告)日：1995-09-21

申请号：DE69021712

申请日：1990-02-08

Applicant: IBM

Inventor： ALAIWAN HAISSAM ,  BASSO CLAUDE ,  CALVIGNAC JEAN ,  COMBES JACQUES ,  KERMAREC FRANCOIS ,  PAUPORTE ANDRE

IPC: G06F11/14 ,  G06F11/20 ,  G06F15/16

Abstract: A checkpointing mechanism implemented in a data processing system comprising a dual processor configuration gives the system a fault tolerance capability while minimizing the complexity of both the software and the hardware. The active and backup processors are coupled asynchronously with some hardware assist functions comprising a memory change detector which captures the memory changes in the memory of the active processor and a mirroring control circuit which causes the memory changes when committed by establish recovery point signals generated by the active processor to be dumped into the memory of the back up processor so that the backup processor can resume the operations of the active processor from the last established recovery point. The active and backup processors may each be connected to a dedicated memory and recovery point storing means, or to a memory including two dual sides shared by all the processors for storing data structures and recovery points.