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    2.
    发明专利
    未知

    公开(公告)号：DE69021712D1

    公开(公告)日：1995-09-21

    申请号：DE69021712

    申请日：1990-02-08

    Applicant: IBM

    Inventor： ALAIWAN HAISSAM ,  BASSO CLAUDE ,  CALVIGNAC JEAN ,  COMBES JACQUES ,  KERMAREC FRANCOIS ,  PAUPORTE ANDRE

    IPC: G06F11/14 ,  G06F11/20 ,  G06F15/16

    Abstract: A checkpointing mechanism implemented in a data processing system comprising a dual processor configuration gives the system a fault tolerance capability while minimizing the complexity of both the software and the hardware. The active and backup processors are coupled asynchronously with some hardware assist functions comprising a memory change detector which captures the memory changes in the memory of the active processor and a mirroring control circuit which causes the memory changes when committed by establish recovery point signals generated by the active processor to be dumped into the memory of the back up processor so that the backup processor can resume the operations of the active processor from the last established recovery point. The active and backup processors may each be connected to a dedicated memory and recovery point storing means, or to a memory including two dual sides shared by all the processors for storing data structures and recovery points.

    Programmable High Performance Data Communication Adapter for High Speed Paquet Transmission Networks
    6.
    发明专利
    Programmable High Performance Data Communication Adapter for High Speed Paquet Transmission Networks 未知

    公开(公告)号：CA2120558A1

    公开(公告)日：1994-12-31

    申请号：CA2120558

    申请日：1994-04-05

    Applicant: IBM

    Inventor： GALAND CLAUDE ,  LEBIZAY GERALD ,  MAUDUIT DANIEL ,  MUNIER JEAN-MARIE ,  PAUPORTE ANDRE ,  SAINT-GEORGES ERIC ,  SPAGNOL VICTOR

    IPC: H04L29/06 ,  H04L12/56

    Abstract: A high performance data packet buffering method and a programmable data communication adapter for high speed packet transmission networks are disclosed. The line adapter includes programmable processing means, for receiving and transmitting data packets of fixed or variable length. This system is characterized in that it comprises means for buffering (132) said data packets, means for identifying said buffering means and said data packets in said buffering means, means for queueing (Figure 15) in storing means (131) said identifying means in a single instruction, means for dequeueing (Figure 16) from said storing (131) means said identifying means in another single instruction , means for releasing said buffering means, Each instruction comprises up to three operations executed in parallel by said processing means : an arithmetical and logical (ALU) operation on said identifying means, a memory operation on said storing means, and a sequence operation.

    8.
    发明专利
    未知

    公开(公告)号：AT144870T

    公开(公告)日：1996-11-15

    申请号：AT93480087

    申请日：1993-06-30

    Applicant: IBM

    Inventor： GALAND CLAUDE ,  MAUDUIT DANIEL ,  PAUPORTE ANDRE ,  SPAGNOL VICTOR ,  LEBIZAY GERALD ,  MUNIER JEAN-MARIE ,  SAINT-GEORGES ERIC

    IPC: H04L29/06

    Abstract: A high performance data packet buffering method and a programmable data communication adapter for high speed packet transmission networks are disclosed. The line adapter includes programmable processing means, for receiving and transmitting data packets of fixed or variable length. This system is characterized in that it comprises means for buffering (132) said data packets, means for identifying said buffering means and said data packets in said buffering means, means for queueing (Figure 15) in storing means (131) said identifying means in a single instruction, means for dequeueing (Figure 16) from said storing (131) means said identifying means in another single instruction , means for releasing said buffering means, Each instruction comprises up to three operations executed in parallel by said processing means : an arithmetical and logical (ALU) operation on said identifying means, a memory operation on said storing means, and a sequence operation.

    9.
    发明专利
    未知

    公开(公告)号：DE69021712T2

    公开(公告)日：1996-04-18

    申请号：DE69021712

    申请日：1990-02-08

    Applicant: IBM

    Inventor： ALAIWAN HAISSAM ,  BASSO CLAUDE ,  CALVIGNAC JEAN ,  COMBES JACQUES ,  KERMAREC FRANCOIS ,  PAUPORTE ANDRE

    IPC: G06F11/14 ,  G06F11/20 ,  G06F15/16

    Abstract: A checkpointing mechanism implemented in a data processing system comprising a dual processor configuration gives the system a fault tolerance capability while minimizing the complexity of both the software and the hardware. The active and backup processors are coupled asynchronously with some hardware assist functions comprising a memory change detector which captures the memory changes in the memory of the active processor and a mirroring control circuit which causes the memory changes when committed by establish recovery point signals generated by the active processor to be dumped into the memory of the back up processor so that the backup processor can resume the operations of the active processor from the last established recovery point. The active and backup processors may each be connected to a dedicated memory and recovery point storing means, or to a memory including two dual sides shared by all the processors for storing data structures and recovery points.

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