公开(公告)号：DE3481872D1

公开(公告)日：1990-05-10

申请号：DE3481872

申请日：1984-12-31

Applicant: IBM

Inventor： COMBES JACQUES ,  ROBBE JEAN-CLAUDE ,  VIALLON PAUL

IPC: G06F9/46 ,  G06F9/48 ,  G06F11/00 ,  G06F11/22 ,  G06F11/30

公开(公告)号：DE69021712D1

公开(公告)日：1995-09-21

申请号：DE69021712

申请日：1990-02-08

Applicant: IBM

Inventor： ALAIWAN HAISSAM ,  BASSO CLAUDE ,  CALVIGNAC JEAN ,  COMBES JACQUES ,  KERMAREC FRANCOIS ,  PAUPORTE ANDRE

IPC: G06F11/14 ,  G06F11/20 ,  G06F15/16

Abstract: A checkpointing mechanism implemented in a data processing system comprising a dual processor configuration gives the system a fault tolerance capability while minimizing the complexity of both the software and the hardware. The active and backup processors are coupled asynchronously with some hardware assist functions comprising a memory change detector which captures the memory changes in the memory of the active processor and a mirroring control circuit which causes the memory changes when committed by establish recovery point signals generated by the active processor to be dumped into the memory of the back up processor so that the backup processor can resume the operations of the active processor from the last established recovery point. The active and backup processors may each be connected to a dedicated memory and recovery point storing means, or to a memory including two dual sides shared by all the processors for storing data structures and recovery points.

公开(公告)号：DE69021712T2

公开(公告)日：1996-04-18

申请号：DE69021712

申请日：1990-02-08

Applicant: IBM

Inventor： ALAIWAN HAISSAM ,  BASSO CLAUDE ,  CALVIGNAC JEAN ,  COMBES JACQUES ,  KERMAREC FRANCOIS ,  PAUPORTE ANDRE

IPC: G06F11/14 ,  G06F11/20 ,  G06F15/16

Abstract: A checkpointing mechanism implemented in a data processing system comprising a dual processor configuration gives the system a fault tolerance capability while minimizing the complexity of both the software and the hardware. The active and backup processors are coupled asynchronously with some hardware assist functions comprising a memory change detector which captures the memory changes in the memory of the active processor and a mirroring control circuit which causes the memory changes when committed by establish recovery point signals generated by the active processor to be dumped into the memory of the back up processor so that the backup processor can resume the operations of the active processor from the last established recovery point. The active and backup processors may each be connected to a dedicated memory and recovery point storing means, or to a memory including two dual sides shared by all the processors for storing data structures and recovery points.

公开(公告)号：CA1236583A

公开(公告)日：1988-05-10

申请号：CA495806

申请日：1985-11-20

Applicant: IBM

Inventor： COMBES JACQUES ,  ROBBE JEAN-CLAUDE ,  VIALLON PAUL

IPC: G06F9/46 ,  G06F9/48 ,  G06F11/00 ,  G06F11/22 ,  G06F11/30

Abstract: Device for detecting the unoperational states of an interrupt driven processor executing instructions on n priority levels, n-1 being the lowest priority level and 0 the highest priority level. It comprises means (18) for dispatching an unoperational state detection task running on the n-1 priority level at time intervals smaller than a specified time-out delay. A detection timer (1) which is set at an initial value each time the task is dispatched and the content of which is changed stepwise once the task has been dispatched and an interval timer (13) having a minimum step value. Means (20) are responsive to the final value taken by the detection timer when the time-out delay has elapsed, to send a level 0 interrupt to the processor. A REMEMBER LATCH (26) is set at the occurrence of the first next pulse from the interval timer if the detection timer is at its final value and which are reset when the level 0 interrupt handling succeeds in restoring the cause of said level 0 interrupt request. Figure 2.