公开(公告)号：US3689803A

公开(公告)日：1972-09-05

申请号：US3689803D

申请日：1971-03-30

Applicant: IBM

Inventor： BAKER THEODORE H ,  TUMAN DANIEL

IPC: H01L21/00 ,  H01L27/02 ,  H01L27/118 ,  H01L19/00

CPC classification number: H01L27/11801 ,  H01L21/00 ,  H01L27/0207

Abstract: A planar monolithic integrated circuit chip containing an isolation region of one conductivity type extending completely around the edge or periphery of the chip in order to insure that there are no exposed P-N junctions on an edge surface of the chip. Such an isolation region extends for at least a minimum distance from the edge of the chip, said distance being determined so as to minimize the risk of any edge defects in the chip resulting from dicing and handling from extending beyond the isolation region into the body of the chip. An insulative layer over the planar surface of the chip supports a metallization pattern for interconnecting the devices in the integrated circuit and for distributing a plurality of voltage supplys at different levels to the devices. The metallization pattern is arranged so that only metallization connected to the voltage supply at the same level as the peripheral isolation region is located on the portion of the insulative layer between the chip edge and the minimum distance of the isolation junction from the edge.

Abstract translation: 一种平面单片集成电路芯片，其包含完全绕芯片的边缘或周边延伸的一种导电类型的隔离区域，以确保在芯片的边缘表​​面上没有暴露的P-N结。 这种隔离区域延伸至少距离芯片边缘的最小距离，所述距离被确定为使由切割和处理引起的芯片中的任何边缘缺陷的风险最小化，从而延伸超出隔离区域进入体内 芯片。 在芯片的平面表面上的绝缘层支持用于互连集成电路中的器件的金属化图案，并用于将不同电平的多个电压源分配到器件。 金属化图案被布置为使得只有与外围隔离区域相同电平的电压源的金属化位于芯片边缘与隔离结与边缘的最小距离之间的绝缘层的部分上。

公开(公告)号：US3922184A

公开(公告)日：1975-11-25

申请号：US42788773

申请日：1973-12-26

Applicant: IBM

Inventor： BAKER THEODORE H ,  GHAFGHAICHI MAJID

IPC: H05K3/46 ,  H01L21/00 ,  H01L21/28 ,  H01L21/306 ,  H01L21/31 ,  H01L21/316 ,  H01L21/3213 ,  H01L21/308

CPC classification number: H01L21/31 ,  H01L21/00 ,  H01L21/316

Abstract: In the fabrication of integrated circuits, a method of forming openings through an insulative layer wherein a plurality of openings being formed through said insulative layer are subjected to two separate etching steps in order to insure that the opening is made. In the method, a layer of electrically insulative material is formed on a substrate. The layer is covered with a first photoresist mask having a plurality of openings. Then, a plurality of openings through the insulative layer coincident with the mask openings is made by applying a chemical etchant through the photoresist mask. The second photoresist mask having a plurality of openings coincident with the openings in the insulative layer is then formed on said layer; these openings in the second photoresist mask have smaller lateral dimensions than the openings in the insulative layer. Thus, the sides of the openings in the insulative layer are masked by photoresist. The chemical etchant is reapplied through the second photoresist mask. In this reapplication, any openings which may not have been fully etched through the insulative layer in the first etching step are now made. On the other hand, because the sides of completed openings are already masked by photoresist, there is no possibility of the reapplied etchant etching through the sides of such completed holes to overetch such holes.

Abstract translation: 在集成电路的制造中，通过绝缘层形成开口的方法，其中通过所述绝缘层形成的多个开口经受两个单独的蚀刻步骤，以确保形成开口。

公开(公告)号：CA1019466A

公开(公告)日：1977-10-18

申请号：CA213807

申请日：1974-11-15

Applicant: IBM

Inventor： BAKER THEODORE H ,  STEVENS RICHARD C ,  TZOU ALBERT J

IPC: H01L21/66 ,  G01R27/02 ,  G01R31/26 ,  H01L21/027 ,  H01L21/28

公开(公告)号：FR2328285A1

公开(公告)日：1977-05-13

申请号：FR7626314

申请日：1976-08-25

Applicant: IBM

Inventor： BAKER THEODORE H ,  GHAFGHAICHI MAJID ,  STEVENS RICHARD C ,  WIMPFHEIMER HANS

IPC: H01L21/3213 ,  H01L21/302 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/3205 ,  H01L21/314 ,  H01L21/94

Abstract: A method of planarizing an electrically insulative layer formed over a non-planar integrated circuit substrate having raised portions. After the electrically insulative layers are deposited over such substrate, the layer has elevations corresponding to the underlying raised portions of the substrate. A masking layer is formed on the electrically insulative layer having at least one opening therethrough coincident with an elevation in the insulative layer; this opening has smaller lateral dimensions than the coincident elevation, thereby facilitating alignment. The elevation in the insulative layer exposed in said at least one opening is then etched to the level of the unelevated portion of the layer, and the insulative layer is then resputtered for a period of time sufficient to planarize the remainder of such etched elevation to the level of the unelevated portions.

公开(公告)号：CA1024663A

公开(公告)日：1978-01-17

申请号：CA213806

申请日：1974-11-15

Applicant: IBM

Inventor： BAKER THEODORE H ,  GHAFGHAICHI MAJID

IPC: H05K3/46 ,  H01L21/00 ,  H01L21/28 ,  H01L21/306 ,  H01L21/31 ,  H01L21/316 ,  H01L21/3213 ,  H01L21/308

Abstract: In the fabrication of integrated circuits, a method of forming openings through an insulative layer wherein a plurality of openings being formed through said insulative layer are subjected to two separate etching steps in order to insure that the opening is made.

公开(公告)号：CA979537A

公开(公告)日：1975-12-09

申请号：CA138126

申请日：1972-03-27

Applicant: IBM

Inventor： BAKER THEODORE H ,  TUMAN DANIEL

IPC: H01L21/00 ,  H01L27/02 ,  H01L27/118

Abstract: A planar monolithic integrated circuit chip containing an isolation region of one conductivity type extending completely around the edge or periphery of the chip in order to insure that there are no exposed P-N junctions on an edge surface of the chip. Such an isolation region extends for at least a minimum distance from the edge of the chip, said distance being determined so as to minimize the risk of any edge defects in the chip resulting from dicing and handling from extending beyond the isolation region into the body of the chip. An insulative layer over the planar surface of the chip supports a metallization pattern for interconnecting the devices in the integrated circuit and for distributing a plurality of voltage supplys at different levels to the devices. The metallization pattern is arranged so that only metallization connected to the voltage supply at the same level as the peripheral isolation region is located on the portion of the insulative layer between the chip edge and the minimum distance of the isolation junction from the edge.

公开(公告)号：CA1067038A

公开(公告)日：1979-11-27

申请号：CA263201

申请日：1976-10-08

Applicant: IBM

Inventor： BAKER THEODORE H ,  GHAFGHAICHI MAJID ,  STEVENS RICHARD C ,  WIMPFHEIMER HANS

IPC: H01L21/3213 ,  H01L21/302 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/3205 ,  C23C15/00

Abstract: PLANARIZING INSULATIVE LAYERS BY RESPUTTERING A method of planarizing an electrically insulative layer formed over a non-planar integrated circuit substrate having raised portions. After the electrically insulative layers are deposited over such substrate, the layer has elevations corresponding to the underlying raised portions of the substrate. A masking layer is formed on the electrically insulative layer having at least one opening therethrough coincident with an elevation in the insulative layer; this opening has smaller lateral dimensions than the coincident elevation, thereby facilitating alignment. The elevation in the insulative layer exposed in said at least one opening is then etched to the level of the unelevated portion of the layer, and the insulative layer is then resputtered for a period of time sufficient to planarize the remainder of such etched elevation to the level of the unelevated portions.

公开(公告)号：CA964771A

公开(公告)日：1975-03-18

申请号：CA135898

申请日：1972-03-01

Applicant: IBM

Inventor： BAKER THEODORE H ,  GHAFGHAICHI MAJID ,  TUMAN DANIEL

IPC: H01L21/00 ,  H01L21/60 ,  H01L27/00