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    1.
    发明专利
    未知

    公开(公告)号：DE2527911A1

    公开(公告)日：1976-01-08

    申请号：DE2527911

    申请日：1975-06-23

    Applicant: IBM

    Inventor： BEAUSOLEIL WILLIAM FRANCIS ,  HILLER RICHARD ,  OTTAWAY GERALD HOWARD ,  WINKLER VAUGHN DONALD

    IPC: G06F7/48 ,  G06K9/46 ,  H03K19/173 ,  H03K19/177 ,  G06K9/06

    Abstract: 1476880 Character recognition programmable logic circuit INTERNATIONAL BUSINESS MACHINES CORP 17 April 1975 [24 June 1974 (2)] 15770/75 Heading G4R A logic circuit arrangement for use in a character recognition device has a shift register SR1- 48 feeding a plurality of programmable logic circuits P AND 1-48. Data representing for instance a scanning matric 40 Î 24 is fed serially to a 960 bit shift register formed of 48 20 bit sections. Each section feeds a plurality of programmable AND circuits 1-48 each of which produces a one bit output which is fed back to 64 feedback latches which also feed the P AND circuits. Selected P AND circuits 37-48 also feed output latches. The P AND circuits may be as shown in Fig. 8C for a three input gate in which latches 115, 116, 124, 125, 133, 134 are set to determine the logic operation. If both latches for an input are zero the inverters, e.g. 119, 120 for input A feed "1"s to AND gate 123. If only one is zero then either A or A is fed to gate 123. OR functions are produced using inverters and de Morgan's theorem A - B = A + B. The shift register may contain dummy registers which are not connected to the logic circuits to reduce the number of connections required while still storing the same number of bits. Thus portions of an area are processed alternately (Fig. 14, not shown).

    4.
    发明专利
    未知

    公开(公告)号：DE1282335B

    公开(公告)日：1968-11-07

    申请号：DEJ0030052

    申请日：1966-02-12

    Applicant: IBM

    Inventor： BEAUSOLEIL WILLIAM FRANCIS ,  D ANTIBES LE CAP ,  HOSKINSON WILLIAM CLIFFORD ,  KING LEWIS EDARD ,  O HERBERT GERHARD WELBER

    IPC: G06F13/10 ,  G06F13/12 ,  G06F15/16 ,  G06F15/17 ,  G06F15/177

    Abstract: 1,119,421. Data processors. INTERNATIONAL BUSINESS MACHINES CORP. 18 Jan., 1966 [16 Feb., 1965], No. 2228/66. Heading G4A. Data is transmitted between two data processing devices via a buffer adapter linked to both devices by data and control channels, which also link the data processing devices to respective groups of input/output devices. Two or more computers are linked together and to input-output (I-O) control units (each controlling one or more input-output devices) by one or more adapters. The channels linking a computer to an adapter comprise a 9-wire data channel (8 bits plus 1 parity bit) from the computer (" bus out "), a similar channel to the computer (" bus in "), tag lines in and out indicating the type of information on the associated bus (e.g. data, address, command, status), various interlock lines, a loop enabling the I-O control units to be scanned in turn, and a suppress out line for preventing presentation of status information or data to the computer. When a first computer (any one) requires to send data to a second computer (any other) it sends the address of the appropriate adapter (priority between adapters is also mentioned) which responds by raising an interlock line to the first computer. The latter drops the address signals whereupon the adapter returns the address to the computer which then sends a write command to the adapter. The adapter attempts to interrupt the second computer. The latter, when ready, issues a sense command to the adapter which in response supplies to the second computer, the (write) command from the first (which was stored in the adapter). The second computer generates a read command and the adapter supplies status information to the first. A comparison is made in the adapter to assure that both computers are not executing the same command. Provided they are not, the adapter signals for successive bytes of data from the first computer and transfers them via a buffer to the second computer. When all the data has been transferred, the first computer issues a stop command to the adapter which generates a status signal and then disconnects from both computers whereupon the latter proceed to scan their respective I-O control units independently. If the comparison (see above) had indicated the same command was being executed, an appropriate status signal would be provided to the initiating computer and the adapter would disconnect. A test I/O command can be used to determine the status of the adapter.

    6.
    发明专利
    未知

    公开(公告)号：DE2333749A1

    公开(公告)日：1974-07-04

    申请号：DE2333749

    申请日：1973-07-03

    Applicant: IBM

    Inventor： BEAUSOLEIL WILLIAM FRANCIS ,  KEEFE GEORGE EDWARD ,  WALKER ERNEST LEE

    IPC: G11C11/14 ,  G01R33/09 ,  G11C19/08 ,  G11C21/00

    Abstract: A plurality of magneto-resistive sensing elements are connected in series and positioned adjacent magnetic bubble domain propagation paths in a compressor circuit. If a data representing bubble is injected into the beginning of the circuit, each bubble already present is forced over to the next idler position. As the bubbles pass the sensing elements their magnetization vectors are rotated producing corresponding changes in the resistance values of the sensors, which may be easily detected as a large magnitude signal indicating the presence of a data bubble.

    MONOLITHIC MEMORIES
    7.
    发明专利
    MONOLITHIC MEMORIES 未知

    公开(公告)号：AU4390772A

    公开(公告)日：1974-01-03

    申请号：AU4390772

    申请日：1972-06-26

    Applicant: IBM

    Inventor： BEAUSOLEIL WILLIAM FRANCIS

    IPC: G06F11/10 ,  G11C29/00 ,  G11C11/34 ,  G11C15/00

    Abstract: A computer memory, most particularly a monolithic memory, may be constructed of components which contain defective bit cells. During the production process, the monolithic chips are sorted into groups in accordance with the chip sector which contains one or more defective cells. The chips are then mounted on memory cards, with all of the chips having a defect in a given chip sector being mounted on a corresponding card sector. The cards, each of which is produced in a substantially identical manner, are then assembled into a complete memory. The address wiring of the memory is provided in such a manner as to ensure that no given memory word, or defined group of bits within a memory word, contains within it more than one memory cell that is known or suspected to be defective. Means are also provided for deriving from the address of any given memory word the bit location within said word of a defective or suspicious bit. In one embodiment shown herein, the suspect bit is bypassed in favor of a redundant bit provided within the memory system. In another embodiment described herein, the suspect bit is utilized just as if it were a good bit, but, upon detection of an error, the suspect bit will be presumed to be in error.

    8.
    发明专利
    未知

    公开(公告)号：DE2230759A1

    公开(公告)日：1973-01-11

    申请号：DE2230759

    申请日：1972-06-23

    Applicant: IBM

    Inventor： BEAUSOLEIL WILLIAM FRANCIS

    IPC: G06F11/10 ,  G11C29/00 ,  G11C7/00

    Abstract: A computer memory, most particularly a monolithic memory, may be constructed of components which contain defective bit cells. During the production process, the monolithic chips are sorted into groups in accordance with the chip sector which contains one or more defective cells. The chips are then mounted on memory cards, with all of the chips having a defect in a given chip sector being mounted on a corresponding card sector. The cards, each of which is produced in a substantially identical manner, are then assembled into a complete memory. The address wiring of the memory is provided in such a manner as to ensure that no given memory word, or defined group of bits within a memory word, contains within it more than one memory cell that is known or suspected to be defective. Means are also provided for deriving from the address of any given memory word the bit location within said word of a defective or suspicious bit. In one embodiment shown herein, the suspect bit is bypassed in favor of a redundant bit provided within the memory system. In another embodiment described herein, the suspect bit is utilized just as if it were a good bit, but, upon detection of an error, the suspect bit will be presumed to be in error.

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