公开(公告)号：JP2001085572A

公开(公告)日：2001-03-30

申请号：JP2000192204

申请日：2000-06-27

Applicant: IBM

Inventor： DONALD S FAAKUHAA ,  CONSTANTINOS I PAPATHOMAS ,  MARK D PORIKUSU

IPC: B32B15/082 ,  C08K3/00 ,  C08L27/12 ,  C08L101/00 ,  H01L23/14 ,  H05K1/02 ,  H05K1/03 ,  H05K3/38 ,  B32B15/08

Abstract: PROBLEM TO BE SOLVED: To provide a low-permittivity dielectric layer which is has satisfactory adhesive property to a conductive layer and is easy to processing. SOLUTION: A printed circuit board has dielectric layers 16, 19, and 23 and dielectric layers 9, 10A, and 12. The dielectric layer 9 is polytetrafluoroethylene in unfillburyl conditions where inorganic particles are dispersed, and it is bonded with thermosetting resin between the conductive layers 19 and 16. A dielectric layer 10A has a structure with the dielectric layer 9 impregnated with thermosetting resin. The thermosetting resin 22 is bonded between the structure 10A and the conductive layer 23 to enhance adhesive property. Since thermosetting resin is formed between the polytetrafluoorethylene, where inorganic particles are dispersed, and the conductive layer, the adhesive property is improved, and stacking at low temperature and low pressure becomes possible.

公开(公告)号：JP2002314253A

公开(公告)日：2002-10-25

申请号：JP2002060395

申请日：2002-03-06

Applicant: IBM

Inventor： JONES GERALD W ,  LAUFFER JOHN M ,  MARKOVICH VOYA R ,  MILLER THOMAS R ,  PAOLLETTI JAMES P ,  CONSTANTINOS I PAPATHOMAS ,  STACK JAMES R

IPC: H05K1/11 ,  H05K3/40 ,  H05K3/46

Abstract: PROBLEM TO BE SOLVED: To provide a method which is newly simplified for forming a multilayer printed wiring board structure having a z-axis interconnection. SOLUTION: For forming a multilayer printed wiring board 10, a plurality of separate layers 12, 14, 16, 18 are shown, and in this example, the board 10 is constituted of four layers in total. As is well known, each layer is originally composed of a dielectric material such as an organic board, and on both surfaces thereof, namely on surfaces 12a, 12b, 14a, 14b, 16a, 16b, 18a, 18b, a suitable circulating plating, namely a wire is provided. As is well known, this is selectively adhered by use of a mask, etc. Each of the layers 12, 14, 16, 18 has a thickness 't' suitably in the range of about 0.50 mm (about 20 mil) to about 2.54 mm (about 100 mil) in correspondence to a size of a hole or a via formed therein.

公开(公告)号：JP2002305367A

公开(公告)日：2002-10-18

申请号：JP2002002614

申请日：2002-01-09

Applicant: IBM

Inventor： DONALD S FAAKUHAA ,  CONSTANTINOS I PAPATHOMAS

IPC: H05K3/28 ,  H01L21/48 ,  H01L23/32 ,  H01L23/498 ,  H05K3/00 ,  H05K3/40 ,  H05K3/42 ,  H05K3/46

Abstract: PROBLEM TO BE SOLVED: To provide a method for burying at least one opening of a semiconductor substrate. SOLUTION: At least one opening of the semiconductor substrate is buried by providing a sacrifice carrier structure on a substrate surface. The sacrifice carrier structure comprises a first layer, a filler material on the first layer, and a mask on the filler material comprising at least one opening. The opening at least partially conforms to the opening of substrate. The filler material is pushed into the opening under heat and pressure, to remove the sacrifice carrier structure.