公开(公告)号：JP2001326470A

公开(公告)日：2001-11-22

申请号：JP2001087939

申请日：2001-03-26

Applicant: IBM

Inventor： DONS FRANCIS J JR ,  FARQUHAR DONALD S ,  FOUST ELIZABETH ,  ROBERT M JAPPU ,  JONES GERALD W ,  JOHN S KURIIJU ,  ROBERT D SEBESUTA ,  DAVID B STONE ,  JAMES R WILCOCKS

IPC: H05K1/02 ,  H01L23/12 ,  H01L23/14 ,  H05K3/46

Abstract: PROBLEM TO BE SOLVED: To provide an electronic package and a method of manufacturing the electronic package. SOLUTION: A package 10 is provided with a semiconductor chip 12 and a multilayer interconnection structure 18 having an allyl surface layer. The semiconductor chip 12 has a plurality of contact members 16 on one surface, and is connected with the inside of the multilayer interconnection structure 18 by using a plurality of solder connecting members 20. The multilayer interconnection structure 18 is constituted so as to electrically and interconnect circuits of a board 100 by using a plurality of other solder connecting members 47 and has a heat conduction layer 22 composed of material having a selected thickness and coefficient of thermal expansion with which solder connecting obstruction between a plurality of first conducting members and the semiconductor chip is prevented totally. The electronic package 10 includes dielectric material having effective tensile stress for ensuring sufficient compliancy with the multilayer interconnection structure 18 during operation. The allyl surface layer has characteristic capable of enduring thermal stress which is generated during heat cycle operation of the electronic package 10.

公开(公告)号：JP2002314253A

公开(公告)日：2002-10-25

申请号：JP2002060395

申请日：2002-03-06

Applicant: IBM

Inventor： JONES GERALD W ,  LAUFFER JOHN M ,  MARKOVICH VOYA R ,  MILLER THOMAS R ,  PAOLLETTI JAMES P ,  CONSTANTINOS I PAPATHOMAS ,  STACK JAMES R

IPC: H05K1/11 ,  H05K3/40 ,  H05K3/46

Abstract: PROBLEM TO BE SOLVED: To provide a method which is newly simplified for forming a multilayer printed wiring board structure having a z-axis interconnection. SOLUTION: For forming a multilayer printed wiring board 10, a plurality of separate layers 12, 14, 16, 18 are shown, and in this example, the board 10 is constituted of four layers in total. As is well known, each layer is originally composed of a dielectric material such as an organic board, and on both surfaces thereof, namely on surfaces 12a, 12b, 14a, 14b, 16a, 16b, 18a, 18b, a suitable circulating plating, namely a wire is provided. As is well known, this is selectively adhered by use of a mask, etc. Each of the layers 12, 14, 16, 18 has a thickness 't' suitably in the range of about 0.50 mm (about 20 mil) to about 2.54 mm (about 100 mil) in correspondence to a size of a hole or a via formed therein.

公开(公告)号：DE10120868A1

公开(公告)日：2001-12-20

申请号：DE10120868

申请日：2001-04-27

Applicant: IBM

Inventor： ALCOE DAVID J ,  DOWNES FRANCIS J ,  JONES GERALD W ,  KRESGE JOHN S ,  TYTRAN-PALOMAKI CHERYL L

IPC: H01L23/498 ,  H05K3/46 ,  H05K3/42

Abstract: Connecting structure comprises a support material (100), a metallic through-hole arranged in the carrier material; a re-distributing layer on a first an a second surface of the carrier material; and a through-contact within the re-distributing layer and selectively arranged above the through-hole and electrically connected to it. Preferred Features: The support material comprises: a base surface (112); a first dielectric material layer (114); a first pair of first signal surfaces (116); a second dielectric material layer (118); a first pair of conducting surfaces (120); a third dielectric material layer (122); a second pair of second signal surfaces (124); a fourth dielectric material layer (126); and a second pair of second conducting surfaces (128). The base surface is a layer of copper-invar-copper. The first and second signal surfaces are impedance-controlled switching circuit layers.

公开(公告)号：HK1040569A1

公开(公告)日：2002-06-14

申请号：HK02101938

申请日：2002-03-13

Applicant: IBM

Inventor： ALCOE DAVID J ,  DOWNES FRANCIS J JR ,  JONES GERALD W ,  KRESGE JOHN S ,  TYTRAN-PALOMAKI CHERYL L

IPC: H01L23/498 ,  H05K3/46 ,  H01L ,  H05K

Abstract: A semiconductor chip carrier having an increased chip connector and plated through hole density. In particular, a substrate having a plurality of plated through holes therein, and a fatigue resistant redistribution layer thereon. The redistribution layer includes a plurality of vias selectively positioned over and contacting the plated through holes. The substrate further including a ground plane, two pair of signal planes, and two pair of power planes, wherein the second pair of power planes are located directly underneath the external dielectric layer. A buried plated through hole within the substrate.