公开(公告)号：JP2004128497A

公开(公告)日：2004-04-22

申请号：JP2003334361

申请日：2003-09-25

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： EGITTO FRANK D ,  FARQUHAR DONALD S ,  MARKOVICH VOYA R ,  MARK D POLIKS ,  POWELL DOUGLAS O

IPC: H01L23/12 ,  G02F1/1347 ,  H01L21/48 ,  H01L23/373 ,  H05K3/46

CPC classification number: H01L21/4853 ,  H01L23/3735 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/114 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4608 ,  H05K3/462 ,  H05K3/4623 ,  H05K3/4626 ,  H05K3/4632 ,  H05K3/4641 ,  H05K3/4688 ,  H05K2201/0141 ,  H05K2201/0191 ,  H05K2201/068 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09554 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/10378 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T156/1092

Abstract: PROBLEM TO BE SOLVED: To provide a multilayer interconnection structure using a LCP dielectric layer and a method for forming the structure. SOLUTION: Each of a first and second LCP (liquid crystal polymer) dielectric layers is bonded directly to each of a first and second opposed layers of a heat conduction layer without an extrinsic adhesive material that bonds the heat conduction layer to either of a first and second LCP dielectric layers. Alternatively, each of a first and second 2S1P substructures is bonded directly to each of a first and second opposed layers of a LCP dielectric bonding layer without an extrinsic adhesive material that bonds the LCP dielectric bonding layer to either of the first and second 2S1P substructures. COPYRIGHT: (C)2004,JPO

Abstract translation: 要解决的问题：提供使用LCP介电层的多层互连结构和形成该结构的方法。 解决方案：第一和第二LCP（液晶聚合物）电介质层中的每一个直接结合到导热层的第一和第二相对层中的每一个，而不需要将导热层粘合到 第一和第二LCP电介质层。 或者，第一和第二2S1P子结构中的每一个直接结合到LCP电介质结合层的第一和第二相对层中的每一个上，而不会将LCP电介质结合层结合到第一和第二2S1P子结构中的任一个的外在粘合材料。 版权所有（C）2004，JPO

公开(公告)号：JP2002314258A

公开(公告)日：2002-10-25

申请号：JP2002075801

申请日：2002-03-19

Applicant: IBM

Inventor： ANSTROM DONALD O ,  CHAMBERLIN BRUCE J ,  LAUFFER JOHN M ,  MARKOVICH VOYA R ,  THOMAS DAVID L

IPC: H01L23/538 ,  H05K1/02 ,  H05K3/46

Abstract: PROBLEM TO BE SOLVED: To provide a method and structure for realizing close wiring, which can exhibit excellent electric characteristics, while satisfying system resistance requirements and characteristic impedance requirements in a printed circuit board applied product or in a chip carrier applied product. SOLUTION: For close wiring, wiring length is selected to enable use of an allowable 'short' wiring as close circuit lines, or short-length wiring lines are provided in a necessary region and switched to possible rough wiring lines of low-resistance. In order to ensure that the resistance of the longest wiring used will not exceed a predetermined maximum resistance, all the wirings are required to have sufficient sectional areas. Provision of a burial via enables change to a low-resistance wiring to form a dense wiring in the element region.

公开(公告)号：JP2002314253A

公开(公告)日：2002-10-25

申请号：JP2002060395

申请日：2002-03-06

Applicant: IBM

Inventor： JONES GERALD W ,  LAUFFER JOHN M ,  MARKOVICH VOYA R ,  MILLER THOMAS R ,  PAOLLETTI JAMES P ,  CONSTANTINOS I PAPATHOMAS ,  STACK JAMES R

IPC: H05K1/11 ,  H05K3/40 ,  H05K3/46

Abstract: PROBLEM TO BE SOLVED: To provide a method which is newly simplified for forming a multilayer printed wiring board structure having a z-axis interconnection. SOLUTION: For forming a multilayer printed wiring board 10, a plurality of separate layers 12, 14, 16, 18 are shown, and in this example, the board 10 is constituted of four layers in total. As is well known, each layer is originally composed of a dielectric material such as an organic board, and on both surfaces thereof, namely on surfaces 12a, 12b, 14a, 14b, 16a, 16b, 18a, 18b, a suitable circulating plating, namely a wire is provided. As is well known, this is selectively adhered by use of a mask, etc. Each of the layers 12, 14, 16, 18 has a thickness 't' suitably in the range of about 0.50 mm (about 20 mil) to about 2.54 mm (about 100 mil) in correspondence to a size of a hole or a via formed therein.

公开(公告)号：DE68917748T2

公开(公告)日：1995-03-30

申请号：DE68917748

申请日：1989-02-02

Applicant: IBM

Inventor： JOHNSON ROBERT W ,  LAWRENCE WILLIAM H ,  LEMON GARY K ,  MAGNUSON ROY H ,  MARKOVICH VOYA R ,  PARSONS RALPH E ,  SAMBUCETTI CARLOS J

IPC: C23C18/18 ,  C23C18/28 ,  C23C18/30 ,  H05K3/00 ,  H05K3/18 ,  H05K3/38 ,  C23C18/16

公开(公告)号：ES2059578T3

公开(公告)日：1994-11-16

申请号：ES89101763

申请日：1989-02-02

Applicant: IBM

Inventor： JOHNSON ROBERT W ,  LAWRENCE WILLIAM H ,  LEMON GARY K ,  MAGNUSON ROY H ,  MARKOVICH VOYA R ,  PARSONS RALPH E ,  SAMBUCETTI CARLOS J

IPC: C23C18/18 ,  C23C18/28 ,  C23C18/30 ,  H05K3/00 ,  H05K3/18 ,  H05K3/38 ,  C23C18/16

公开(公告)号：DE69402448D1

公开(公告)日：1997-05-15

申请号：DE69402448

申请日：1994-01-27

Applicant: IBM

Inventor： ALPAUGH WARREN A ,  MARKOVICH VOYA R ,  TRIVEDI AJIT K ,  ZARR RICHARD S

IPC: H01L23/12 ,  H01L23/50 ,  H01L23/538 ,  H05K1/02 ,  H05K1/11 ,  H05K3/00 ,  H05K3/42 ,  H05K3/46

Abstract: A printed circuit board or card for direct chip attachment that includes at least one power core (P1), at least one signal plane (51) that is adjacent to the power core, and plated through holes (11) for electrical connection is provided. In addition, a layer of dielectric material (13) is adjacent the power core and a circuitized conductive layer (12, 14) is adjacent the dielectric material, followed by a layer of photosensitive dielectric material (15) adjacent the conductive layer. Photodeveloped blind vias (17) for subsequent connection to the power core and drilled blind vias (18) for subsequent connection to the signal plane are provided. Also provided is process for fabricating the printed circuit board or card for direct chip attachment.

公开(公告)号：DE69402448T2

公开(公告)日：1997-09-25

申请号：DE69402448

申请日：1994-01-27

Applicant: IBM

Inventor： ALPAUGH WARREN A ,  MARKOVICH VOYA R ,  TRIVEDI AJIT K ,  ZARR RICHARD S

IPC: H01L23/12 ,  H01L23/50 ,  H01L23/538 ,  H05K1/02 ,  H05K1/11 ,  H05K3/00 ,  H05K3/42 ,  H05K3/46

Abstract: A printed circuit board or card for direct chip attachment that includes at least one power core (P1), at least one signal plane (51) that is adjacent to the power core, and plated through holes (11) for electrical connection is provided. In addition, a layer of dielectric material (13) is adjacent the power core and a circuitized conductive layer (12, 14) is adjacent the dielectric material, followed by a layer of photosensitive dielectric material (15) adjacent the conductive layer. Photodeveloped blind vias (17) for subsequent connection to the power core and drilled blind vias (18) for subsequent connection to the signal plane are provided. Also provided is process for fabricating the printed circuit board or card for direct chip attachment.

公开(公告)号：CA2120557A1

公开(公告)日：1994-12-12

申请号：CA2120557

申请日：1994-04-05

Applicant: IBM

Inventor： ANSCHEL MORRIS ,  INGRAHAM ANTHONY P ,  LAMB CHARLES R ,  LOWELL MICHAEL D ,  MARKOVICH VOYA R ,  MAYR WOLFGANG ,  MURPHY RICHARD G ,  PIERSON MARK V ,  POWERS TAMAR A ,  RENY TIMOTHY S ,  REYNOLDS SCOTT D ,  SAMMAKIA BAHGAT G ,  STORR WAYNE R

IPC: G01R31/26 ,  G01R31/28 ,  H01L21/66 ,  H01R13/02

Abstract: METHOD AND APPARATUS FOR TESTING OF INTEGRATED CIRCUIT CHIPS A method of testing semi-conductor chips is disclosed. The individual semiconductor chips have I/O, power, and ground contacts. In the method of the invention a chip test fixture system is provided. The chip test fixture system has contacts corresponding to the contacts on the semiconductor chip. The carrier contacts have dendritic surfaces. The chip contacts are brought into electrically conductive contact with the conductor pads on the chip test fixture system. Test signal input vectors are applied to the inputs of the semiconductor chip, and output signal vectors are recovered from the semiconductor chip. After testing the chip is removed from the substrate.

公开(公告)号：CA1332885C

公开(公告)日：1994-11-08

申请号：CA581531

申请日：1988-10-27

Applicant: IBM

Inventor： JOHNSON ROBERT W ,  LAWRENCE WILLIAM H ,  LEMON GARY K ,  MAGNUSON ROY H ,  MARKOVICH VOYA R ,  PARSONS RALPH E ,  SAMBUCETTI CARLOS J

IPC: C23C18/18 ,  C23C18/28 ,  C23C18/30 ,  H05K3/00 ,  H05K3/18 ,  H05K3/38 ,  C23C18/16

Abstract: A non-conductive substrate is conditioned for subsequent selective deposition of a metal thereon by providing at least one of the major surfaces of the substrate in roughened form, contacting that surface(s) with a palladium/tin catalyst, activating the catalyst by employing an alkali hydroxide solution, laminating a photosensitive composition to the major surface(s), and exposing the photosensitive composition to actinic light in a predetermined pattern and then developing to provide the predetermined pattern.

公开(公告)号：CA2110472A1

公开(公告)日：1994-09-02

申请号：CA2110472

申请日：1993-12-01

Applicant: IBM

Inventor： BHATT ANILKUMAR C ,  BUDA LEO R ,  EDWARDS ROBERT D ,  HART PAUL J ,  INGRAHAM ANTHONY P ,  MARKOVICH VOYA R ,  MOLLA JAYNAL A ,  MURPHY RICHARD G ,  SAXENMEYER GEORGE J JR ,  WALKER GEORGE F ,  WHALEN BETTE J ,  ZARR RICHARD S

IPC: G01R31/28 ,  H01L21/60 ,  H01L21/66 ,  G01R31/26

Abstract: A method of testing semiconductor chips is disclosed. The individual semiconductor chips have I/O, power, and ground contacts. In the method of the invention a chip carrier is provided. The chip carrier has contacts corresponding to the contacts on the semiconductor chip. The carrier contacts have dendritic surfaces. The chip contacts are brought into conductive contact with the conductor pads on the chip carrier. Test signal input vectors are applied to the inputs of the semiconductor chip, and output signal vectors are recovered from the semiconductor chip. After testing, the chip may be removed from the substrate. Alternatively, the chip may be bonded through the dendritic conductor pads to the substrate after successful testing.