公开(公告)号：DE3787073D1

公开(公告)日：1993-09-23

申请号：DE3787073

申请日：1987-10-02

Applicant: IBM

Inventor： FINLAY DAVID ERNEST ,  HANNA STEPHEN DALE ,  STEVENSON DAVID CRAIG ,  VARGA JOHN THOMAS

IPC: G06K15/00 ,  B41J2/485 ,  B41J5/30 ,  G06F3/12 ,  G06K15/02 ,  G09G5/24 ,  G06K15/12

Abstract: A character generator with multidirectional scan and variable line and character (or symbol) size capability is disclosed. Universality is implemented by producing a serial binary stream which can be used to print or display in any of eight combinations of scan direction and progression, that is, for scan direction left to right, or vice versa, progressing up or down, or scan direction top to bottom or vice versa, progressing left or right. In formatting the serial binary stream, a font is accessed (for basic symbol definition), which selectively provides for orthogonal scans of the symbol definitions. Variable line size is implemented by terminating a symbol row (or line) based on a predetermined size criteria regardless of the comparable font dimension and "filling" up to the line size to the extent the corresponding font dimension is less than the predetermined size criteria. Variable character (or symbol) size is implemented by independently multiplying the effect of a symbol definition by selected (integral) factors, in orthogonal directions. The general architecture includes a font table (for symbol definition), an address/escape (A/E) table, defining symbol size for comparison with line size parameters, a character position escape (CPE) table to define a leading character or symbol on each line and a page buffer (PB) memory defining the characters (symbols) in the document and their relationship with other characters (symbols). Access to the CPE table allows access to the PB, from there to the A/E table and from there to the font allows extraction of selected and appropriate portions of the symbol definition to make up the binary system.

公开(公告)号：DE3786526T2

公开(公告)日：1994-02-17

申请号：DE3786526

申请日：1987-10-02

Applicant: IBM

Inventor： DOMINQUES RUBEN ,  LOPEZ JESUS CABRERA ,  FINLAY DAVID ERNEST ,  STEVENSON DAVID CRAIG ,  HANNA STEPHEN DALE ,  ZEGAFUSE DONALD WARD

IPC: G06K15/00 ,  B41J2/485 ,  G06F3/12 ,  G06K15/02 ,  G09G1/14 ,  G09G5/22 ,  G06K15/12

Abstract: A character generator with multidirectional scan and variable line and character (or symbol) size capability is disclosed. Universality is implemented by producing a serial binary stream which can be used to print or display in any of eight combinations of scan direction and progression, that is, for scan direction left to right, or vice versa, progressing up or down, or scan direction top to bottom or vice versa, progressing left or right. In formatting the serial binary stream, a font is accessed (for basic symbol definition), which selectively provides for orthogonal scans of the symbol definitions. Variable line size is implemented by terminating a symbol row (or line) based on a predetermined size criteria regardless of the comparable font dimension and "filling" up to the line size to the extent the corresponding font dimension is less than the predetermined size criteria. Variable character (or symbol) size is implemented by independently multiplying the effect of a symbol definition by selected (integral) factors, in orthogonal directions. The general architecture includes a font table (for symbol definition), an address/escape (A/E) table, defining symbol size for comparison with line size parameters, a character position escape (CPE) table to define a leading character or symbol on each line and a page buffer (PB) memory defining the characters (symbols) in the document and their relationship with other characters (symbols). Access to the CPE table allows access to the PB, from there to the A/E table and from there to the font allows extraction of selected and appropriate portions of the symbol definition to make up the binary system.

公开(公告)号：AU2887477A

公开(公告)日：1979-03-22

申请号：AU2887477

申请日：1977-09-16

Applicant: IBM

Inventor： FINLAY DAVID ERNEST

IPC: G06F9/46 ,  G06F9/445 ,  G06F12/02 ,  G06F12/06 ,  G06F13/12 ,  G06F9/20 ,  G06F9/10 ,  G03G21/00 ,  G03G15/00 ,  G05B15/00

Abstract: A programmable controller includes a random access memory for storing signals relating to a plurality of programs executable in the controller. A portion of the memory addressing is zoned for enabling one or more programs to have exclusive access to that zone. The addressability of input/output registers, diagnostic registers and selected other units of common interest to all such programs are addressable in each of the plurality of zones as if such registers were uniquely assigned to such respective memory zones.

公开(公告)号：DE3580739D1

公开(公告)日：1991-01-10

申请号：DE3580739

申请日：1985-09-24

Applicant: IBM

Inventor： FINLAY DAVID ERNEST ,  LOPEZ JESUS CABRERA ,  MERENESS THOMAS SETH

IPC: G06F3/12 ,  B41J2/485 ,  G06K15/00 ,  G09G5/00 ,  G09G5/36 ,  G09G5/393 ,  H04N1/21 ,  H04N1/387

公开(公告)号：DE2743284A1

公开(公告)日：1978-04-06

申请号：DE2743284

申请日：1977-09-27

Applicant: IBM

Inventor： FINLAY DAVID ERNEST

IPC: G06F9/46 ,  G06F9/445 ,  G06F12/02 ,  G06F12/06 ,  G06F13/12 ,  G11C7/00 ,  G06F9/18 ,  G06F13/00

Abstract: A programmable controller includes a random access memory for storing signals relating to a plurality of programs executable in the controller. A portion of the memory addressing is zoned for enabling one or more programs to have exclusive access to that zone. The addressability of input/output registers, diagnostic registers and selected other units of common interest to all such programs are addressable in each of the plurality of zones as if such registers were uniquely assigned to such respective memory zones.

公开(公告)号：DE3787073T2

公开(公告)日：1994-03-17

申请号：DE3787073

申请日：1987-10-02

Applicant: IBM

Inventor： FINLAY DAVID ERNEST ,  HANNA STEPHEN DALE ,  STEVENSON DAVID CRAIG ,  VARGA JOHN THOMAS

IPC: G06K15/00 ,  B41J2/485 ,  B41J5/30 ,  G06F3/12 ,  G06K15/02 ,  G09G5/24 ,  G06K15/12

Abstract: A character generator with multidirectional scan and variable line and character (or symbol) size capability is disclosed. Universality is implemented by producing a serial binary stream which can be used to print or display in any of eight combinations of scan direction and progression, that is, for scan direction left to right, or vice versa, progressing up or down, or scan direction top to bottom or vice versa, progressing left or right. In formatting the serial binary stream, a font is accessed (for basic symbol definition), which selectively provides for orthogonal scans of the symbol definitions. Variable line size is implemented by terminating a symbol row (or line) based on a predetermined size criteria regardless of the comparable font dimension and "filling" up to the line size to the extent the corresponding font dimension is less than the predetermined size criteria. Variable character (or symbol) size is implemented by independently multiplying the effect of a symbol definition by selected (integral) factors, in orthogonal directions. The general architecture includes a font table (for symbol definition), an address/escape (A/E) table, defining symbol size for comparison with line size parameters, a character position escape (CPE) table to define a leading character or symbol on each line and a page buffer (PB) memory defining the characters (symbols) in the document and their relationship with other characters (symbols). Access to the CPE table allows access to the PB, from there to the A/E table and from there to the font allows extraction of selected and appropriate portions of the symbol definition to make up the binary system.

公开(公告)号：DE3786526D1

公开(公告)日：1993-08-19

申请号：DE3786526

申请日：1987-10-02

Applicant: IBM

Inventor： DOMINQUES RUBEN ,  LOPEZ JESUS CABRERA ,  FINLAY DAVID ERNEST ,  STEVENSON DAVID CRAIG ,  HANNA STEPHEN DALE ,  ZEGAFUSE DONALD WARD

IPC: G06K15/00 ,  B41J2/485 ,  G06F3/12 ,  G06K15/02 ,  G09G1/14 ,  G09G5/22 ,  G06K15/12

Abstract: A character generator with multidirectional scan and variable line and character (or symbol) size capability is disclosed. Universality is implemented by producing a serial binary stream which can be used to print or display in any of eight combinations of scan direction and progression, that is, for scan direction left to right, or vice versa, progressing up or down, or scan direction top to bottom or vice versa, progressing left or right. In formatting the serial binary stream, a font is accessed (for basic symbol definition), which selectively provides for orthogonal scans of the symbol definitions. Variable line size is implemented by terminating a symbol row (or line) based on a predetermined size criteria regardless of the comparable font dimension and "filling" up to the line size to the extent the corresponding font dimension is less than the predetermined size criteria. Variable character (or symbol) size is implemented by independently multiplying the effect of a symbol definition by selected (integral) factors, in orthogonal directions. The general architecture includes a font table (for symbol definition), an address/escape (A/E) table, defining symbol size for comparison with line size parameters, a character position escape (CPE) table to define a leading character or symbol on each line and a page buffer (PB) memory defining the characters (symbols) in the document and their relationship with other characters (symbols). Access to the CPE table allows access to the PB, from there to the A/E table and from there to the font allows extraction of selected and appropriate portions of the symbol definition to make up the binary system.

公开(公告)号：DE3484218D1

公开(公告)日：1991-04-11

申请号：DE3484218

申请日：1984-09-10

Applicant: IBM

Inventor： FINLAY DAVID ERNEST ,  NORGREN KENT STEVEN ,  SHOOK FRANKIE SHERWOOD

IPC: G06F13/42 ,  G06F13/16

Abstract: An interface circuit for connecting a memory controller (208) to either a synchronous bus or an asynchronous bus. The interface circuit comprises switch means (197) for supplying a signal indicative of the type of bus and synchronizing means (198) for synchronizing memory access request signals with a local clock when the interface circuit is coupled to an asynchronous bus. An interface method of connecting memory circuits to either a synchronous bus or an asynchronous bus. The method comprises the generation of a mode signal indicative of the type of bus, and the synchronization of the memory access request signals with a local clock when the mode signals indicate an asynchronous bus.