公开(公告)号：GB2455406A

公开(公告)日：2009-06-10

申请号：GB0821864

申请日：2008-12-01

Applicant: IBM

Inventor： FUCHS THOMAS ,  KOEHLER THOMAS ,  SCHLECHTER SIEGMUND

IPC: G06F12/10 ,  G06F9/38 ,  G06F12/1027

Abstract: A memory attached accelerator has a micro architecture comprising at least one co-processor separated from at least one core processor, wherein the co-processor directly uses the instructions of the core processor and directly accesses a main storage using virtual addresses of the core processor. The co-processor includes a Translation Lookaside Buffer (TLB) that preferably comprises at least one entry in the form of tag information stored in a tag register which assigns a virtual address to an absolute memory address. The TLB is preferably divided into compartments of a specified number of entries, each compartment holding translations for a consecutive set of pages representing a data compression dictionary. The tag information is maintained only for the starting page of the dictionary and is loaded and compared only once per operation. In the case of a TLB hit, the respective absolute address is sent to a dedicated cache for fetching the data.

公开(公告)号：GB2524516A

公开(公告)日：2015-09-30

申请号：GB201405315

申请日：2014-03-25

Applicant: IBM

Inventor： VOGT JOERG-STEPHAN ,  JACOBI CHRISTIAN ,  RIEKE REINER ,  FUCHS THOMAS

IPC: H03M7/30

Abstract: A system for data compression has a multi-stage pipeline structure 113 and a distributed memory comprising a main hash table 101 and at least one victim hash table 103. The system concurrently writes an uncompressed data element 105 in the main hash table using a first address 115 generated by a first hash function 107 on the data element, and reads a first data element 109 from the main hash table using the first address, so as to avoid a collision. The system then concurrently writes the first data element to the victim hash table using a second address 117 generated by a second hash function 111 on the first data element, and reads a second data 120 element from the victim hash table using a third address 121generated by the second hash function on the uncompressed data element. The first or second data element is selected depending on which has the longest match to the uncompressed data element, and is used for providing a compressed format with backward reference to the longest match.

公开(公告)号：GB2524515A

公开(公告)日：2015-09-30

申请号：GB201405314

申请日：2014-03-25

Applicant: IBM

Inventor： VOGT JOERG-STEPHAN ,  FUCHS THOMAS ,  JACOBI CHRISTIAN ,  SOFIA ANTHONY T

IPC: H03M7/30

Abstract: An output sequence of data elements 203 representing a sequence of input data elements 201 in compressed format, each output data element comprising a backward reference 207 to matched strings, is further processed by an extended matcher to improve the compression ratio. The extended matcher identifies a backward reference in a selected output data element, selects the string to which it refers and then combines it with strings of one or more subsequent output data elements to form one or more combined strings. The extended matcher then looks for a sequence in the stored input data elements matching at least part of the one or more the combined strings, and selects a combined string having the longest matching sequence. The backward reference of the output data element is then redefined 217 by the extended matcher to indicate the new longest matching sequence. The compression system may have a multi-stage pipeline structure. The compression may be LZ77.

公开(公告)号：GB2523188A

公开(公告)日：2015-08-19

申请号：GB201402849

申请日：2014-02-18

Applicant: IBM

Inventor： SCHROEDER FRIEDRICH ,  BOERSMA MAARTEN ,  FUCHS THOMAS ,  LANG DAVID

IPC: G06F17/50

Abstract: An improved method and system are provided for pipeline depth exploration in a register transfer level design description of an electronic circuit. The method comprises providing a list of input registers and output registers for the circuit design to be modified S100, traversing output connections paths for each input register and replacing any register in the output connection paths by a respective wire unless the register is contained in the list of output registers S110. An initial total cycle time value for the modified registerless circuit design is determined, accounting for a register latch insertion delay time value S120. A gate level description for the modified circuit design is obtained by macro synthesis with the initial total cycle time value S130, and the total cycle time value for the modified circuit design is varied to determine theoretical limit of the modified circuit design S140. The theoretical limit of the modified circuit design is realized when negative slacks are present in the macro synthesis of the gate level description for the modified circuit design with the corresponding total cycle time value S150. The pipeline depth of the circuit design may be reduced, if said total cycle time value of the modified circuit design is lower than a threshold.