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    DYNAMIC ADDRESS TRANSLATION WITH FETCH PROTECTION
    4.
    发明申请
    DYNAMIC ADDRESS TRANSLATION WITH FETCH PROTECTION 审中-公开
    具有保护功能的动态地址转换

    公开(公告)号：WO2009087133A9

    公开(公告)日：2009-09-24

    申请号：PCT/EP2009050050

    申请日：2009-01-05

    Applicant: IBM ,  GREINER DAN ,  GAINEY CHARLES JR ,  HELLER LISA ,  OSISEK DAMIAN ,  PFEFFER ERWIN ,  SLEGEL TIMOTHY ,  WEBB CHARLES

    Inventor： GREINER DAN ,  GAINEY CHARLES JR ,  HELLER LISA ,  OSISEK DAMIAN ,  PFEFFER ERWIN ,  SLEGEL TIMOTHY ,  WEBB CHARLES

    IPC: G06F12/14 ,  G06F12/10

    CPC classification number: G06F12/1027 ,  G06F9/30047 ,  G06F12/0215 ,  G06F12/1009 ,  G06F12/1036 ,  G06F12/145 ,  G06F2212/1052 ,  G06F2212/654 ,  G06F2212/656 ,  G06F2212/68

    Abstract: What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated is first obtained and an initial origin address of a translation table of the hierarchy of translation tables is obtained. Based on the obtained initial origin, a segment table entry is obtained. The segment table entry is configured to contain a format control and access validity fields. If the format control and access validity fields are enabled, the segment table entry further contains an access control field, a fetch protection field, and a segment-frame absolute address. Store operations are permitted only if the access control field matches a program access key provided by any one of a Program Status Word or an operand of a program instruction being executed. Fetch operations are permitted if the program access key associated with the virtual address is equal to the segment access control field.

    Abstract translation: 提供的是增强的动态地址转换设施。 在一个实施例中，首先获得要被翻译的虚拟地址，并且获得翻译表层级的翻译表的初始起始地址。 基于获得的初始起点，获得段表条目。 段表项被配置为包含格式控制和访问有效性字段。 如果启用格式控制和访问有效性字段，则段表条目还包含访问控制字段，提取保护字段和段帧绝对地址。 仅当访问控制字段与程序状态字或正在执行的程序指令的操作数提供的程序访问键匹配时，才允许存储操作。 如果与虚拟地址相关联的程序访问密钥等于段访问控制字段，则允许获取操作。

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    5.
    发明专利
    "Compare and Delay"-Befehle 未知

    公开(公告)号：DE112015000203B4

    公开(公告)日：2024-12-05

    申请号：DE112015000203

    申请日：2015-02-23

    Applicant: IBM

    Inventor： GREINER DAN ,  SLEGEL TIMOTHY ,  JACOBI CHRISTIAN ,  SCHMIDT DONALD WILLIAM ,  MITRAN MARCEL ,  GAINEY CHARLES JR

    IPC: G06F9/52 ,  G06F9/30 ,  G06F9/38 ,  G06F9/455

    Abstract: Bereitgestellt wird eine Verzögerungseinrichtung, in der eine Programmausführung verzögert werden kann, bis ein vordefiniertes Ereignis eintritt, z.B. bis ein Vergleich von Arbeitsspeicherpositionen eine wahre Bedingung ergibt, eine Zeitüberschreitung erreicht wird, eine Unterbrechung ausgesetzt wird oder eine andere Bedingung gegeben ist. Die Verzögerungseinrichtung beinhaltet einen oder mehrere „Compare and Delay“-Maschinenbefehle, mit denen eine Ausführung verzögert wird. Der eine oder die mehreren „Compare and Delay“-Befehle können einen 32-Bit-„Compare and Delay“-Befehl (CAD-Befehl) und einen 64-Bit-„Compare and Delay“-Befehl (CADG-Befehl) beinhalten.

    DYNAMIC ENABLEMENT OF MULTITHREADING
    8.
    发明专利
    DYNAMIC ENABLEMENT OF MULTITHREADING 未知

    公开(公告)号：CA2940905A1

    公开(公告)日：2015-10-01

    申请号：CA2940905

    申请日：2015-03-19

    Applicant: IBM

    Inventor： GREINER DAN ,  FARRELL MARK ,  OSISEK DAMIAN LEO ,  SCHMIDT DONALD WILLIAM ,  BUSABA FADI YUSUF ,  KUBALA JEFFREY PAUL ,  BRADBURY JONATHAN DAVID ,  HELLER LISA CRANTON ,  SLEGEL TIMOTHY ,  GAINEY CHARLES JR ,  JACOBI CHRISTIAN

    IPC: G06F9/46 ,  G06F9/50

    Abstract: Embodiments relate to dynamic enablement of multithreading. According to an aspect, a computer system includes a configuration with a core configurable between a single thread (ST) mode and a multithreading (MT) mode. The ST mode addresses a primary thread, and the MT mode addresses the primary thread and one or more secondary threads on shared resources of the core. The computer system also includes a multithreading facility configured to control the configuration to perform a method. The method includes executing in the primary thread in the ST mode, an MT mode setting instruction. A number of threads requested is obtained from a location specified by the MT mode setting instruction. Based on determining that the number of threads requested indicates multiple threads, the MT mode is enabled to execute the multiple threads including the primary thread and the one or more secondary threads.

    CONVERT FROM ZONED FORMAT TO DECIMAL FLOATING POINT FORMAT
    10.
    发明专利
    CONVERT FROM ZONED FORMAT TO DECIMAL FLOATING POINT FORMAT 未知

    公开(公告)号：CA2852862A1

    公开(公告)日：2013-07-04

    申请号：CA2852862

    申请日：2012-11-13

    Applicant: IBM

    Inventor： CARLOUGH STEVEN ,  SCHWARZ ERIC MARK ,  SLEGEL TIMOTHY ,  GAINEY CHARLES JR ,  MITRAN MARCEL ,  COPELAND REID

    IPC: G06F9/30 ,  G06F9/318

    Abstract: Machine instructions, referred to herein as a long Convert from Zoned instruction (CDZT) and extended Convert from Zoned instruction (CXZT), are provided that read EBCDIC or ASCII data from memory, convert it to the appropriate decimal floating point format, and write it to a target floating point register or floating point register pair. Further, machine instructions, referred to herein as a long Convert to Zoned instruction (CZDT) and extended Convert to Zoned instruction (CZXT), are provided that convert a decimal floating point (DFP) operand in a source floating point register or floating point register pair to EBCDIC or ASCII data and store it to a target memory location.

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