公开(公告)号：EP0814507A1

公开(公告)日：1997-12-29

申请号：EP97304339

申请日：1997-06-20

Applicant: SIEMENS AG ,  IBM

Inventor： HAMMERL ERWIN ,  MANDELMAN JACK A ,  POSCHENRIEDER BERNHARD ,  SHORT ALVIN P ,  SRINIVASAN RADHIKA ,  STENGL REINHARD J ,  HO HERBERT L

IPC: H01L27/00 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108

CPC classification number: H01L27/10861 ,  H01L27/10832

Abstract: Method for forming three-dimensional device structures such as a trench capacitor DRAM cell comprising a second device (370) formed over a first device (315) is disclosed. A layer (350,355) having a single crystalline top surface (350) is formed above the first device (315) to provide the base for forming the active area of the second device.

Abstract translation: 公开了一种用于形成三维器件结构的方法，例如包括形成在第一器件（315）上的第二器件（370）的沟槽电容器DRAM单元。 具有单晶顶表面（350）的层（350,355）形成在第一装置（315）上方，以提供用于形成第二装置的有效区域的基座。

公开(公告)号：EP0794567A3

公开(公告)日：2000-01-12

申请号：EP97102901

申请日：1997-02-21

Applicant: SIEMENS AG ,  IBM

Inventor： HO HERBERT L ,  SRINIVASAN RADHIKA ,  HALLE SCOTT D ,  HAMMERL ERWIN ,  DOBUZINSKY DAVID M ,  MANDELMAN JACK A ,  JASO MARK ANTHONY

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/762 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/70

CPC classification number: H01L27/10861 ,  H01L21/76232 ,  H01L27/10832 ,  H01L28/82 ,  Y10S438/973

Abstract: A simplified method of fabricating a storage node for a deep trench-based DRAM on a semiconductor substrate. The method involves the etching a trench in a surface of the substrate and then forming a layer of dielectric material on a sidewall of the trench the top portion of which is subsequently removed from the sidewall. Next, a layer of oxide is grown on the exposed portion of the sidewall. A portion of this layer of oxide is then removed from the sidewall in order to orient the layer of oxide a predetermined distance from the surface of the substrate. Finally, the trench is filled with a semiconductive material.

公开(公告)号：JP2000228442A

公开(公告)日：2000-08-15

申请号：JP2000025509

申请日：2000-02-02

Applicant: IBM ,  SIEMENS AG

Inventor： HO HERBERT ,  SRINIVASAN RADHIKA ,  HAMMERL ERWIN ,  AGAHI FARID ,  BRONNER GARY ,  FLIETNER BERTRAND

IPC: H01L21/76 ,  H01L21/762

Abstract: PROBLEM TO BE SOLVED: To reduce parasitic leak of a shallow trench isolation via. SOLUTION: A distance between a silicon nitride liner 43 and an active silicon sidewall is increased by depositing an insulation oxide layer 20 prior to depositing of the silicon nitride liner 43. Preferably, the insulation oxide layer 20 comprises tetraethyl orthosilicate. The method includes formation of one or a plurality of shallow trench isolations inside a semiconductor wafer through etching, sticking of an insulation oxide layer 20 inside a trench, formation of thermal oxide 25 inside a trench and sticking of the silicon nitride liner 43 inside a trench. The thermal oxide 25 can be formed before or after the insulation oxide layer 20 is deposited.

公开(公告)号：JPH1074907A

公开(公告)日：1998-03-17

申请号：JP16576497

申请日：1997-06-23

Applicant: SIEMENS AG ,  IBM

Inventor： HAMMERL ERWIN ,  MANDELMAN JACK A ,  POSCHENRIEDER BERNHARD ,  SHORT ALVIN P ,  SRINIVASAN RADHIKA ,  STENGL REINHARD J ,  HO HERBERT L

IPC: H01L27/00 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: A device layout has a device structure including a first device and a second device formed thereon, and an active region of the second region is located inside the upper surface so as to facilitate a three-dimensional device layout. SOLUTION: For example, a highly doped N polylayer is next formed on the surface. This polylayer is planarized up to an upper surface of a gate 895 to form a bit-line contact area 110. An MO dielectric layer is layed to expose the contact area 110. A metal layer 150 is next deposited so as to fill an contact opening 120. This metal layer 150 is etched for forming a bit-line conductor. The capacity of spatially positioning a device on a trench allows a more effective three-dimensional layout. As a result, the density of a device for a prescribed area can be increased.

公开(公告)号：JPH1041465A

公开(公告)日：1998-02-13

申请号：JP10727497

申请日：1997-04-24

Applicant: IBM ,  SIEMENS AG

Inventor： DOBUZINSKY DAVID MARK ,  FUGARDI STEPHEN GERARD ,  HAMMERL ERWIN ,  HO HERBERT LEI ,  RAMAC SAMUEL C ,  STRONG ALVIN WAYNE

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/822

Abstract: PROBLEM TO BE SOLVED: To manufacture a high resistance resistor by using materials and a method common the those used for the integrated circuit process. SOLUTION: As a method for manufacturing a resistor element for an integrated circuit semiconductor device, and insulation film 120 formed is silicon nitride and the like is deposited first. Then, a a film 130 containing titanium is deposited on the insulation film 120. The film 130 and the insulation film 120 are heat-treated so as the diffuse titanium in the insulation film 120. As a result, titanium is diffused in the insulation film 120. Thus, a resistor element with relatively high resistance is manufactured. The merit of this method is that it can be easily integrated with the conventional integrated circuit manufacturing technologies.

公开(公告)号：JPH11145415A

公开(公告)日：1999-05-28

申请号：JP24707098

申请日：1998-09-01

Applicant: SIEMENS AG ,  IBM

Inventor： HAMMERL ERWIN ,  MANDELMAN JACK A ,  SHORT ALVIN P ,  STENGL REINHARD J ,  HO HERBERT L ,  POSCHENRIEDER BERNHARD ,  SRINIVASAN RADHIKA

IPC: H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a method of forming a second device of a transistor, for example, on first device of a trench, for example, in the manufacture of a dynamic random access memory using a three-dimensional trench capacitor. SOLUTION: A layer having an uppermost face of a single crystal is formed on a first device, and a layer 2 is used as a base for forming an active region of a second device. In this case, a substrate 305 having a single-crystal structure and the flat substrate surface is prepared, and a trench capacitor 315 is manufacture in the substrate. A polysilicon layer in the capacitor 315 is bored in the part lower than the substrate surface to form a recessed part, and an intermediate layer is formed in the recessed part to a height larger than the surface of a pad. This intermediate layer has the uppermost face of the single crystal. The surface of the intermediate layer and the pad are planarized in such a way that the uppermost surface of the intermediate layer substantially becomes flat to the substrate surface and a transistor 370 is manufactured on the uppermost face of the single crystal.

公开(公告)号：JPH10214889A

公开(公告)日：1998-08-11

申请号：JP2253198

申请日：1998-01-21

Applicant: SIEMENS AG ,  IBM

Inventor： HO HERBERT ,  HAMMERL ERWIN ,  DOBUZINSKY DAVID M ,  PALM J HERBERT ,  FUGARDI STEPHEN ,  AJMERA ATUL ,  MOSEMAN JAMES F ,  RAMAC SAMUEL C

IPC: H01L21/76 ,  H01L21/318

Abstract: PROBLEM TO BE SOLVED: To contain a trapping center with a lower density than before conversion, by depositing an Si3 N4 covering with a specific thickness in an STI structure by the low-pressure chemical vapor deposition method, performing speedy heat annealing under specific conditions immediately after depositing the covering, and converting Si3 N4 from amorphous to a crystal material. SOLUTION: After a shallow trench is etched, a thin thermal oxide with a thickness of approximately 10nm is grown to eliminate an etching damage. Then, an Si3 N4 covering with a thickness of 5-10nm is deposited on the upper surface of an oxide layer in amorphous state at a temperature of 720-780 deg.C in a shallow trench isolation structure(STI). Then, immediately after the covering is deposited, a high-speed heat annealing is executed nearly for 60 seconds at 1,050-1,150 deg.C in pure nitrogen or ammonium and the Si3 N4 covering is converted from the amorphous state to the crystal material state of a low- temperature-hexagonal (d) Si3 N4 phase.

公开(公告)号：DE69504252D1

公开(公告)日：1998-10-01

申请号：DE69504252

申请日：1995-06-09

Applicant: IBM

Inventor： FAHEY PAUL MARTIN ,  MORIKADO MUTSUO ,  HAMMERL ERWIN ,  HO HERBERT LEI

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/76 ,  H01L21/762 ,  H01L21/763

公开(公告)号：DE69737469T2

公开(公告)日：2007-11-29

申请号：DE69737469

申请日：1997-04-24

Applicant: SIEMENS AG ,  IBM

Inventor： DOBUZINSKY DAVID MARK ,  FUGARDI STEPHEN GERARD ,  HAMMERL ERWIN ,  HO HERBERT LEI ,  RAMAC SAMUEL C ,  STRONG ALVIN WAYNE

IPC: H01L21/3205 ,  H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8244

Abstract: According to the preferred embodiment of the present invention, an improved resistor and method of fabrication is provided. The method for fabricating a resistive element into an integrated circuit semiconductor device comprises the steps of: depositing a dielectric film, such as silicon nitride; depositing a titanium film upon the dielectric film; and annealing the titanium and dielectric films. This causes titanium to be diffused into the dielectric film. This creates a resistive element having a relatively high resistivity. The preferred embodiment method has the advantage of being easily integrated into conventional integrated circuit fabrication techniques.

公开(公告)号：AT518240T

公开(公告)日：2011-08-15

申请号：AT00101726

申请日：2000-01-27

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： HO HERBERT ,  SRINIVASAN RADHIKA ,  HAMMERL ERWIN ,  AGAHI FARID ,  BRONNER GARY ,  FLIETNER BERTRAND

IPC: H01L21/76 ,  H01L21/762

Abstract: A reduction in parasitic leakages of shallow trench isolation vias is disclosed wherein the distance between the silicon nitride liner and the active silicon sidewalls is increased by depositing an insulating oxide layer prior to deposition of the silicon nitride liner. Preferably, the insulating oxide layer comprises tetraethylorthosilicate. The method comprises of etching one or more shallow trench isolations into a semiconductor wafer; depositing an insulating oxide layer into the trench; growing a thermal oxide in the trench; and depositing a silicon nitride liner in the trench. The thermal oxide may be grown prior to or after deposition of the insulating oxide layer.