1.
    发明专利
    未知

    公开(公告)号:DE3586035D1

    公开(公告)日:1992-06-17

    申请号:DE3586035

    申请日:1985-10-23

    Applicant: IBM

    Abstract: The present invention relates to apparatus for encoding and decoding a stream of randomly distributed binary bits representing digital data of the type comprising encoding means (10) for encoding the stream of binary bits, recording means (18) for recording representations of the encoded stream of binary bits and recovery means (20, 25) for recovering timing signals and a stream of data signals from the recorded representations. … The apparatus is characterised in that the encoding means (10) achieves a run length limited, partial response coding of the data stream, and the recovery means comprises a first partial response decoder (20) for recovering a timing signal from the recorded representations, and a second partial response decoder (22) and a constrained decoder (24) means for recovering a stream of data signals from the recorded representations. … The present invention also relates to a method of encoding and decoding a stream of randomly distributed binary bits representing digital data using apparatus as above.

    METHOD AND APPARATUS FOR GENERATING A NOISELESS SLIDING BLOCK CODE FOR A (2,7) CHANNEL WITH RATE 1/2

    公开(公告)号:DE3269690D1

    公开(公告)日:1986-04-10

    申请号:DE3269690

    申请日:1982-11-05

    Applicant: IBM

    Abstract: An algorithm and the hardware embodiment for producing a run length limited code useful in magnetic recording channels are described. The system described produces sequences which have a minimum of 2 zeros and a maximum of 7 zeros between adjacent 1's. The code is generated by a sequential scheme that maps 1 bit of unconstrained into 2 bits of constrained data. The encoder is a finite state machine whose internal state description requires 3 bits. It possesses the attractive feature of reset data blocks which reset it to a fixed state. The decoder requires a lookahead of three future channel symbols (6 bits) and its operation is channel state independent. The error propagation due to a random error is 3 bits. The hardware implementation is extremely simple and can operate at very high data speeds.

    MODULAR IMPLEMENTATION FOR A PARALLELIZED KEY EQUATION SOLVER FOR LINEAR ALGEBRAIC CODES

    公开(公告)号:CA2057666A1

    公开(公告)日:1992-07-23

    申请号:CA2057666

    申请日:1991-12-13

    Applicant: IBM

    Abstract: SA9-91-003 Apparatus and method for implementing a parallelized algorithm for solving the key equation for the decoding of a linear algebraic code. A computational loop has one branching condition that branches into two straight-line loops. One of these executes three multiplication operations and the other executes five multiplication operations, 2t iterations of these two loops being required to decode t symbols in error. These loops are coupled such that during each successive 2t iterations, four multiplication operations are executed simultaneously in pairs, the fifth multiplication operation in said other loop being paired with a multiplication operation in the next iteration of said one loop. During one of the paired multiplication operations an inverse table look up operation is executed, and during another of the multiplication operations an addition operation is executed.

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