公开(公告)号：JPS6353785A

公开(公告)日：1988-03-08

申请号：JP9551587

申请日：1987-04-20

Applicant: IBM

Inventor： HELWIG KLAUS ,  LOHLEIN WOLFDIETER ,  TONG MINH H

IPC: G11C11/408 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04

公开(公告)号：DE60123542T2

公开(公告)日：2007-05-10

申请号：DE60123542

申请日：2001-08-23

Applicant: IBM

Inventor： HELWIG KLAUS

IPC: G11C15/04

Abstract: Power consumption is reduced in a content addressable memory of a data processing system or a data processor. The content addressable memory includes at least a first single bit storage ( 101; 301 ), a word line (WL), at least one bit write line (BLWT, BLWC) and a hit/miss line (H/M), and at least a first single bit compare circuit ( 201; 320 ), the first single bit storage including at least a first output (A; A 0 ) and the first single bit compare circuit including at least a first compare bit input (BLCT; CB 0 ) and two field effect transistors ( 113, 114; 312, 313 ). In order to reduce the power consumption, the first output (A; A 0 ) of the single bit storage ( 101; 301 ) is applied to the gate of only one, a first field effect transistor ( 114; 312 ) of the two field effect transistors ( 113, 114; 312, 313 ). For an additional reduction of the power consumption, two single bit storages ( 101, 301 ) are connected to a shared compare circuit ( 319 ). In case of a mismatch, only one out of four compare nodes (C 0 , C 1 , C 2 , C 3 ) of the shared compare circuit is switched high, i.e. changes its potential.

公开(公告)号：DE3685654D1

公开(公告)日：1992-07-16

申请号：DE3685654

申请日：1986-08-22

Applicant: IBM

Inventor： HELWIG KLAUS ,  LOHLEIN WOLFDIETER ,  TONG MINH H

IPC: G11C11/408 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G06F11/20

Abstract: Externally generated addresses are fed simultaneously to the two decoders of a memory and to a comparator which also receives fuse addresses, corresponding to redundant word and/or bit lines. In the event of a match signal between external and fuse addresses the redundant word line is activated and all unselected word or bit lines are held. A restore operation for the address decoder is then initiated by switching on the addressing clock. The unselected word or bit lines are held in this condition by a clamp signal which deactivates the address decorder and initiates a restore operation. For a read operation the word or bit line potential is prevented from dropping to earth potential by early disconnection of the selected word or bit line.

公开(公告)号：CA2006228C

公开(公告)日：1994-10-25

申请号：CA2006228

申请日：1989-12-20

Applicant: IBM

Inventor： DAO-TRONG SON ,  GETZLAFF KLAUS J ,  HELWIG KLAUS

IPC: G06F7/533 ,  G06F7/52 ,  G06F7/53 ,  G06F9/302

Abstract: A multiplier for multiplying two binary operands comprising an encoding unit, a multiplying unit composed of two multiplying arrays and a logic unit. The encoding unit to which a second operand is supplied generates factors following the Booth algorithm. The two multiplying arrays are respectively supplied with a first operand and factors belonging to the higher significance digits, respectively, of the second operand. Both multiplying arrays simultaneously multiply the factors with the first operand into respective partial end products. Both partial end products are applied to the logic unit which generates therefrom the end product in accordance with the algorithm used at the beginning.

公开(公告)号：BR9000776A

公开(公告)日：1991-01-22

申请号：BR9000776

申请日：1990-02-20

Applicant: IBM

Inventor： DAO-TRONG SON ,  GETZLAFF KLAUS JOERG ,  HELWIG KLAUS

IPC: G06F7/533 ,  G06F7/52 ,  G06F7/53

公开(公告)号：DE60123542D1

公开(公告)日：2006-11-16

申请号：DE60123542

申请日：2001-08-23

Applicant: IBM

Inventor： HELWIG KLAUS

IPC: G11C15/04

Abstract: Power consumption is reduced in a content addressable memory of a data processing system or a data processor. The content addressable memory includes at least a first single bit storage ( 101; 301 ), a word line (WL), at least one bit write line (BLWT, BLWC) and a hit/miss line (H/M), and at least a first single bit compare circuit ( 201; 320 ), the first single bit storage including at least a first output (A; A 0 ) and the first single bit compare circuit including at least a first compare bit input (BLCT; CB 0 ) and two field effect transistors ( 113, 114; 312, 313 ). In order to reduce the power consumption, the first output (A; A 0 ) of the single bit storage ( 101; 301 ) is applied to the gate of only one, a first field effect transistor ( 114; 312 ) of the two field effect transistors ( 113, 114; 312, 313 ). For an additional reduction of the power consumption, two single bit storages ( 101, 301 ) are connected to a shared compare circuit ( 319 ). In case of a mismatch, only one out of four compare nodes (C 0 , C 1 , C 2 , C 3 ) of the shared compare circuit is switched high, i.e. changes its potential.

公开(公告)号：AT341818T

公开(公告)日：2006-10-15

申请号：AT01120228

申请日：2001-08-23

Applicant: IBM

Inventor： HELWIG KLAUS

IPC: G11C15/04

Abstract: Power consumption is reduced in a content addressable memory of a data processing system or a data processor. The content addressable memory includes at least a first single bit storage ( 101; 301 ), a word line (WL), at least one bit write line (BLWT, BLWC) and a hit/miss line (H/M), and at least a first single bit compare circuit ( 201; 320 ), the first single bit storage including at least a first output (A; A 0 ) and the first single bit compare circuit including at least a first compare bit input (BLCT; CB 0 ) and two field effect transistors ( 113, 114; 312, 313 ). In order to reduce the power consumption, the first output (A; A 0 ) of the single bit storage ( 101; 301 ) is applied to the gate of only one, a first field effect transistor ( 114; 312 ) of the two field effect transistors ( 113, 114; 312, 313 ). For an additional reduction of the power consumption, two single bit storages ( 101, 301 ) are connected to a shared compare circuit ( 319 ). In case of a mismatch, only one out of four compare nodes (C 0 , C 1 , C 2 , C 3 ) of the shared compare circuit is switched high, i.e. changes its potential.