公开(公告)号：SG85714A1

公开(公告)日：2002-01-15

申请号：SG200003913

申请日：2000-07-13

Applicant: IBM

Inventor： GARY BELA BRONNER ,  JEFFREY PETER GAMBINO ,  CARL J RADENS

IPC: H01L21/027 ,  H01L21/28 ,  H01L21/304 ,  B24B37/04 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/10 ,  H01L21/70 ,  H01L21/335

Abstract: A method of forming a semiconductor device, including forming a substrate with a memory array region and a logic device region, growing a thick gate dielectric over the substrate, forming a gate stack, including a first polysilicon layer, over the thick gate dielectric for the memory array region, forming a thin gate dielectric on the substrate over the logic device region, wherein layers of the gate stack in the memory array region protect the thick gate oxide during the forming of the thin gate dielectric, forming a second polysilicon layer for the gate stack in the logic device region, to produce a resulting structure, wherein a thickness of the second polysilicon layer is at least as thick as the gate stack in the memory array region, planarizing the structure using chemical mechanical polishing (CMP), and patterning the gate stacks in said memory array region and the logic device region.

公开(公告)号：SG108827A1

公开(公告)日：2005-02-28

申请号：SG200106036

申请日：2001-10-01

Applicant: IBM

Inventor： JAMES W ADKISSON ,  RAMACHANDRA DIVAKARUNI ,  JEFFREY PETER GAMBINO ,  JACK ALLAN MANDELMAN

IPC: H01L27/10 ,  H01L21/8242 ,  H01L21/84 ,  H01L27/108 ,  H01L27/12 ,  H01L23/538

Abstract: A semiconductor device is presented which is directed to a method of forming embedded DRAM and logic devices, where the DRAM devices are formed in bulk, single crystalline semiconductor regions (24) and logic devices are formed in silicon-on-insulator ("SOI") regions (26) and where buried, doped glass to smooth the 250 nm step at the edge of the DRAM array region, making it easier to perform the lithography used to pattern the deep trenches (32) for storage in the bulk region. The resulting structure is also disclosed.