公开(公告)号：JP2013201449A

公开(公告)日：2013-10-03

申请号：JP2013115224

申请日：2013-05-31

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Machines Corporation

Inventor： ETHAN HARRISON CANNON ,  FURUKAWA TOSHIHARU ,  JOHN GERARD GAUDIELLO ,  HACKNEY MARC CHARLES ,  STEVEN JOHN HOLMES ,  DAVID VACLAV HORAK ,  CHARLES WILLIAM KOBURGER III ,  JACK ALLAN MANDELMAN ,  WILLIAM ROBERT TONTI

IPC: H01L27/12 ,  H01L21/02 ,  H01L21/20 ,  H01L21/265 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092

CPC classification number: H01L21/76264

Abstract: PROBLEM TO BE SOLVED: To provide a method of forming a semiconductor structure.SOLUTION: The method comprises the steps of: bonding a first dielectric layer on a first semiconductor layer with a second dielectric layer on a second semiconductor layer; defining a plurality of openings extending from a top surface of the first semiconductor layer to the second semiconductor layer; applying dielectric regions to sidewalls of each of the openings; epitaxially growing an island of semiconductor material of the second semiconductor layer to fill each of the openings; forming an insulating layer at a given depth that divides the first semiconductor layer into a plurality of device regions between the insulating layer and the top surface and a plurality of body regions between the insulating layer and the first and second dielectric layers such that each of the body regions is aligned with one of the device regions between an adjacent pair of the dielectric regions; forming shallow trench isolation regions extending from the top surface of the first semiconductor layer; and forming a contact through each of the shallow trench isolation regions to the body regions.

Abstract translation: 要解决的问题：提供一种形成半导体结构的方法。解决方案：该方法包括以下步骤：在第二半导体层上将第一介电层与第二介电层接合在第一半导体层上; 限定从所述第一半导体层的顶表面延伸到所述第二半导体层的多个开口; 将介质区域施加到每个开口的侧壁; 外延生长第二半导体层的半导体材料岛以填充每个开口; 在给定的深度处形成绝缘层，所述绝缘层将所述第一半导体层划分成所述绝缘层和所述顶表面之间的多个器件区域以及所述绝缘层与所述第一和第二电介质层之间的多个体区域，使得 身体区域与相邻的一对电介质区域之间的器件区域之一对准; 形成从第一半导体层的顶表面延伸的浅沟槽隔离区; 以及通过每个浅沟槽隔离区域形成到身体区域的接触。

公开(公告)号：MY116040A

公开(公告)日：2003-10-31

申请号：MYPI19993047

申请日：1999-07-20

Applicant: IBM

Inventor： FARIBORZ ASSADERAGHI ,  CLAUDE L BERTIN ,  JEFFREY P GAMBINO ,  LOUIS LU-CHEN HSU ,  JACK ALLAN MANDELMAN

IPC: H01L21/8242 ,  H01L21/336 ,  H01L21/84 ,  H01L27/108 ,  H01L23/52 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786

Abstract: AN ACTIVE FET BODY DEVICE WHICH COMPRISES AN ACTIVE FET REGION INCLUDING A GATE (13, 15, 16,24,26,28,30,3 I), A BODY REGION (4) AND ELECTRICAL CONNECTION BETWEEN SAID GATE AND SAID BODY REGION THAT IS LOCATED WITHIN THE ACTIVE FET REGION IS PROVIDED ALONG WITH VARIOUS METHODS FOR FABRICATING THE DEVICES. THE ELECTRICAL CONNECTION EXTENDS OVER SUBSTANTIALLY THE ENTIRE WIDTH OF THE FET. (FIGURE 6)

公开(公告)号：SG85712A1

公开(公告)日：2002-01-15

申请号：SG200003706

申请日：2000-06-28

Applicant: IBM

Inventor： MICHAEL J HARGROVE ,  JACK ALLAN MANDELMAN

IPC: H01L21/28 ,  H01L21/768 ,  H01L23/522 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786 ,  H01L21/84

Abstract: A structure and process for making a semiconductor device with SOI body contacts under the gate conductor. The gate conductor is partitioned into segments and provides a body contact under each gate conductor segment over the width of the device. A plurality of body contacts may be distributed across the length of the gate conductor. This results in a relatively short path for holes leaving the body to traverse and allows accumulated charge to be removed from the body region under the gate. The structure provides for stable and efficient body-contact operation for SOI MOSFETS of any width operating at high speeds.

公开(公告)号：SG94845A1

公开(公告)日：2003-03-18

申请号：SG200103937

申请日：2001-06-28

Applicant: IBM

Inventor： LAWRENCE ALFRED CLEVENGER ,  JACK ALLAN MANDELMAN ,  RAJARAO JAMMY ,  OLEG GLUSCHENKOV ,  IRENE LENNOX MCSTAY ,  KWONG-HON WONG ,  JONATHAN FALTERMEIER

IPC: H01L29/43 ,  H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

Abstract: A gate structure is disclosed for a semiconductor device, and particularly a MOSFET for such applications as CMOS technology. The gate structure entails an electrical insulating layer 14 on a semiconductor substrate 12, over which a polysilicon gate electrode 16 is formed. The gate structure further includes a gate conductor 18 that is electrically connected with the gate electrode through a diffusion barrier layer 20 having semi-insulating properties. The composition and thickness of the diffusion barrier layer are tailored so that the barrier layer is effective to block diffusion and intermixing between the gate conductor and polysilicon gate electrode, yet provides sufficient capacitive coupling and/or current leakage so as not to significantly increase the gate propagation delay of the gate structure.

公开(公告)号：SG91923A1

公开(公告)日：2002-10-15

申请号：SG200102773

申请日：2001-05-10

Applicant: IBM

Inventor： CLAUDE LOUIS BERTIN ,  RAMACHANDRA DIVAKARUNI ,  RUSSELL J HOUGHTON ,  JACK ALLAN MANDELMAN ,  WILLIAM ROBERT PATRICK TONTI

IPC: H01L21/82 ,  H01L21/334 ,  H01L23/525 ,  H01L27/108 ,  H01L27/12 ,  H01L21/84

Abstract: An anti-fuse structure that can be programmed at low voltage and current and which potentially consumes very little chip spaces and can be formed interstitially between elements spaced by a minimum lithographic feature size is formed on a composite substrate such as a silicon-on-insulator wafer by etching a contact through an insulator to a support semiconductor layer, preferably in combination with formation of a capacitor-like structure reaching to or into the support layer. The anti-fuse may be programmed either by the selected location of conductor formation and/or damaging a dielectric of the capacitor-like structure. An insulating collar is used to surround a portion of either the conductor or the capacitor-like structure to confine damage to the desired location. Heating effects voltage and noise due to programming currents are effectively isolated to the bulk silicon layer, permitting programming during normal operation of the device. Thus the potential for self-repair without interruption of operation is realized.

公开(公告)号：SG108827A1

公开(公告)日：2005-02-28

申请号：SG200106036

申请日：2001-10-01

Applicant: IBM

Inventor： JAMES W ADKISSON ,  RAMACHANDRA DIVAKARUNI ,  JEFFREY PETER GAMBINO ,  JACK ALLAN MANDELMAN

IPC: H01L27/10 ,  H01L21/8242 ,  H01L21/84 ,  H01L27/108 ,  H01L27/12 ,  H01L23/538

Abstract: A semiconductor device is presented which is directed to a method of forming embedded DRAM and logic devices, where the DRAM devices are formed in bulk, single crystalline semiconductor regions (24) and logic devices are formed in silicon-on-insulator ("SOI") regions (26) and where buried, doped glass to smooth the 250 nm step at the edge of the DRAM array region, making it easier to perform the lithography used to pattern the deep trenches (32) for storage in the bulk region. The resulting structure is also disclosed.

公开(公告)号：SG84601A1

公开(公告)日：2001-11-20

申请号：SG200002902

申请日：2000-05-26

Applicant: IBM

Inventor： JACK ALLAN MANDELMAN ,  GARY BELA BRONNER ,  RAMACHANDRA DIVAKARUNI

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/092 ,  H01L27/10 ,  H01L27/108 ,  H01L29/78 ,  H01L21/22

Abstract: A method for providing dual work function doping and borderless array diffusion contacts includes providing a semiconductor substrate, a gate insulator, a conductor on the gate insulator, an insulating cap on the conductor and insulating spacers on sidewalls of a portion of the conductor and the insulating cap. The method also includes doping portions of the semiconductor substrate and the conductor with a first conductive type and other portions with a second conductive type. The conductor may be annealed such that dopants of the first and second conductive types spread over the respective conductors.