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    Associative store
    1.
    发明授权
    Associative store 失效
    关联店

    公开(公告)号：US3890603A

    公开(公告)日：1975-06-17

    申请号：US45498274

    申请日：1974-03-26

    Applicant: IBM

    Inventor： JONES JOHN W ,  SEARS JOHN F ,  TAYLOR KEITH G

    IPC: G11C15/04 ,  G11C15/00

    CPC classification number: G11C15/046

    Abstract: An associative store, particularly designed for performance of logic by table-look-up, has fixed search and read fields. Input to the search field is through an encoder which converts sets of plural binary inputs into one out of K set of drive signals, where K is an integer related to the number of bits in each set. Output signals from the read field are decoded by exclusive-ors corresponding ordered bit positions of two read arrays. The search field is either conventionally addressed for loading or read-only.

    Abstract translation: 一个特别设计用于通过表查找执行逻辑的关联存储库具有固定的搜索和读取字段。 搜索字段的输入是通过编码器将多组二进制输入的集合转换为K组驱动信号中的一组，其中K是与每组中位数相关的整数。 来自读取字段的输出信号通过两个读取阵列的排他位对应的有序位位置进行解码。 常规寻址搜索字段用于加载或只读。

    UNIVERSAL LSI ARRAY LOGIC MODULES WITH INTEGRAL STORAGE ARRAY AND VARIABLE AUTONOMOUS SEQUENCING
    3.
    发明专利
    UNIVERSAL LSI ARRAY LOGIC MODULES WITH INTEGRAL STORAGE ARRAY AND VARIABLE AUTONOMOUS SEQUENCING 未知

    公开(公告)号：CA1047165A

    公开(公告)日：1979-01-23

    申请号：CA224378

    申请日：1975-04-09

    Applicant: IBM

    Inventor： JONES JOHN W

    IPC: G06F7/00 ,  G06F7/57 ,  G06F7/575 ,  G06F9/22 ,  G06F9/26 ,  G06F9/40 ,  G06F11/20 ,  G06F15/78 ,  H03K19/177 ,  G11C7/00

    Abstract: UNIVERSAL LSI ARRAY LOGIC MODULES WITH INTEGRAL STORAGE ARRAY AND VARIABLE AUTONOMOUS SEQUENCING A universal array logic module featuring autonomous operation includes interconnected array structured logic and a small writable storage array. The module is subject to large scale integrated packaging as a standardly dimensioned unit (e.g. chip). The internal connections form discrete first and second internal circulation loops in one of which the storage array connects as a serial constituent randomly addressable by signals carried in the other loop. The storage array typically holds eight 32-bit words. The logic arrays may be read-only structures organized to perform arithmetic and translational logic manipulations under autonomous (internal) control. The module assembly includes integral input/output gating for transferring signals between an external bus and the internal loops. The logic array structure permits both external and internal control of cyclic operation. The operation repertoire includes interrupts, resets, and sequence branches. Interrupted status (loop signals) is saved in predetermined address locations of the storage array, requiring novel manipulation and storage of the address argument of the interrupted cycle. The logic arrays may be economically configured as read-only structures.

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