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    1.
    发明专利
    未知

    公开(公告)号：DE69004932T2

    公开(公告)日：1994-05-19

    申请号：DE69004932

    申请日：1990-06-01

    Applicant: IBM

    Inventor： KERBAUGH MICHAEL L ,  KOBURGER III CHARLES W ,  MACHESNEY BRIAN J

    IPC: H01L21/76 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/762

    Abstract: A method of forming a planarized dielectric filled wide shallow trench (14) in a semiconductor substrate (10) is provided. A layer of etch stop (12) such as Si3N4 is deposited onto the semiconductor substrate (10), and wide trenches (14) are formed through the Si3N4 into the substrate (10) by conventional RIE. The surface of the substrate (10) including the trenches (14) have formed thereon a SiO2 coating (18), conforming to the surface of the substrate (10). A layer of etch resistant material (20) such as polysilicon is deposited onto the SiO2 material (18). The polysilicon (20) outside the width of the trenches (14) is then removed by chemical-mechanical polishing to expose the SiO2 there below, while leaving the SiO2 above the trenches (14) covered with polysilicon (20). The exposed SiO2 is then RIE etched down to the Si , leaving a plug of SiO2 capped with the etch resistant polysilicon (20) over each trench (14). These plugs are then removed by mechanical polishing down to the Si3N4, to provide a planarized upper surface of SiO2 and Si on the top of the substrate (10). The invention also is useful in forming planarized surfaces on substrates (10) having trenches (14) filled with conductive material.

    2.
    发明专利
    未知

    公开(公告)号：DE69004932D1

    公开(公告)日：1994-01-13

    申请号：DE69004932

    申请日：1990-06-01

    Applicant: IBM

    Inventor： KERBAUGH MICHAEL L ,  KOBURGER III CHARLES W ,  MACHESNEY BRIAN J

    IPC: H01L21/76 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/762

    Abstract: A method of forming a planarized dielectric filled wide shallow trench (14) in a semiconductor substrate (10) is provided. A layer of etch stop (12) such as Si3N4 is deposited onto the semiconductor substrate (10), and wide trenches (14) are formed through the Si3N4 into the substrate (10) by conventional RIE. The surface of the substrate (10) including the trenches (14) have formed thereon a SiO2 coating (18), conforming to the surface of the substrate (10). A layer of etch resistant material (20) such as polysilicon is deposited onto the SiO2 material (18). The polysilicon (20) outside the width of the trenches (14) is then removed by chemical-mechanical polishing to expose the SiO2 there below, while leaving the SiO2 above the trenches (14) covered with polysilicon (20). The exposed SiO2 is then RIE etched down to the Si , leaving a plug of SiO2 capped with the etch resistant polysilicon (20) over each trench (14). These plugs are then removed by mechanical polishing down to the Si3N4, to provide a planarized upper surface of SiO2 and Si on the top of the substrate (10). The invention also is useful in forming planarized surfaces on substrates (10) having trenches (14) filled with conductive material.

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