公开(公告)号：GB2602405A

公开(公告)日：2022-06-29

申请号：GB202203285

申请日：2020-08-07

Applicant: IBM

Inventor： RAZVAN FIGULI ,  STEFAN PAYER ,  CEDRIC LICHTENAU ,  KERSTIN SCHELM

IPC: G06F11/07

Abstract: A method for detecting faults in substring search operations includes providing, using a processor unit including vector registers of M vector elements each, anMxM Matrix of comparators for characterwise comparison of the elements of a reference string stored in a first one of the vector registers and a target string stored in a second one of the vector registers. A vector element is an n-bit element for encoding a character.A resulting bit vector is generated using comparison performed by the MxM matrix. The resulting bit vector indicates characters of the target string that fully match the reference string and indicates characters of the target string that partially match the reference string. Fault detection in the substring search operations is performed by utilizing the resulting bit vector.

公开(公告)号：GB2630547A

公开(公告)日：2024-11-27

申请号：GB202412923

申请日：2023-03-21

Applicant: IBM

Inventor： MICHAEL KLEIN ,  PETRA LEBER ,  CEDRIC LICHTENAU ,  STEFAN PAYER ,  KERSTIN SCHELM

IPC: G06F7/483 ,  G06F7/499 ,  G06F7/74

Abstract: Rounding hexadecimal floating point numbers using binary incrementors, including: incrementing, by a first incrementor, a first subset of bits of an operand comprising a binary hexadecimal floating point operand; incrementing, by a second incrementor, a second subset of bits of the operand; generate an intermediate result based on a carryout of the second incrementor; and generate an incremented result based on a carryout of the first incrementor and one or more of: a first bit of the intermediate result or the carryout of the second incrementor.

公开(公告)号：GB2630547B

公开(公告)日：2025-04-09

申请号：GB202412923

申请日：2023-03-21

Applicant: IBM

Inventor： MICHAEL KLEIN ,  PETRA LEBER ,  CEDRIC LICHTENAU ,  STEFAN PAYER ,  KERSTIN SCHELM

IPC: G06F7/483 ,  G06F7/499 ,  G06F7/74

Abstract: Rounding hexadecimal floating point numbers using binary incrementors, including: incrementing, by a first incrementor, a first subset of bits of an operand comprising a binary hexadecimal floating point operand; incrementing, by a second incrementor, a second subset of bits of the operand; generate an intermediate result based on a carryout of the second incrementor; and generate an incremented result based on a carryout of the first incrementor and one or more of: a first bit of the intermediate result or the carryout of the second incrementor.

公开(公告)号：GB2527125B

公开(公告)日：2021-01-20

申请号：GB201410591

申请日：2014-06-13

Applicant: IBM

Inventor： KERSTIN SCHELM ,  SILVIA MELITTA MUELLER ,  MANUELA NIEKISCH ,  MICHAEL KROENER

IPC: G06F7/487 ,  G06F7/537

Abstract: Performing an arithmetic operation in a data processing unit, including calculating a number of iterations for performing the arithmetic operation with a given number of bits per iteration. The number of bits per iteration is a positive natural number. A number of consecutive digit positions of a digit in a sequence of bits represented in the data processing unit is counted. The length of the sequence is a multiple of the number of bits per iteration. A quotient of the number of consecutive digit positions divided by the number of bits per iteration is calculated, as well as a remainder of the division.

公开(公告)号：GB2530990A

公开(公告)日：2016-04-13

申请号：GB201417582

申请日：2014-10-06

Applicant: IBM

Inventor： MICHAEL KROENER ,  SILVIA MELITTA MUELLER ,  STEVEN R CARLOUGH ,  MICHAEL KLEIN ,  KERSTIN SCHELM ,  PETRA LEBER ,  JUERGEN HAESS

IPC: G06F7/485 ,  G06F7/491

Abstract: A decimal floating point unit for performing add or subtract calculations on a first (100) and second operand (101) comprising unpacking S200 the first and second operand such as by formatting 128 bit width mantissa to be 136 bit wide; conditionally swapping S202 the first and second operand, if an exponent (104) of the first operand is less than an exponent (105) of the second operand, and aligning S204, S206 the operands based on the exponent difference and a number of leading zeroes in the operand with the larger exponent. Adding or subtracting the operands S208 is performed on the aligned operands with normalizing and rounding of the result which is then packed S210. Binary floating point arithmetic can also be performed on the decimal floating point unit which may be pipelined.