公开(公告)号：IL284709D0

公开(公告)日：2021-08-31

申请号：IL28470921

申请日：2021-07-08

Applicant: IBM ,  CEDRIC LICHTENAU ,  JONATHAN D BRADBURY ,  ERIC M SCHWARZ ,  RAZVAN PETER FIGULI ,  STEFAN PAYER

Inventor： CEDRIC LICHTENAU ,  JONATHAN D BRADBURY ,  ERIC M SCHWARZ ,  RAZVAN PETER FIGULI ,  STEFAN PAYER

IPC: G06F16/903 ,  G06F17/16 ,  G06F40/205

Abstract: An instruction is provided for performing a vector string search. The instruction to be processed is obtained, with the instruction being defined to be a string search instruction to locate occurrence of a substring within a string. The instruction is processed, with the processing including searching the string specified in one operand of the instruction using the substring specified in another operand of the instruction. Based on the searching locating a first full match of the substring within the string, a full match condition indication is returned with position of the first full match in the string, and based on the searching locating only a partial match of the substring at a termination of the string, a partial match condition indication is returned, with the position of the partial match in the string.

公开(公告)号：GB2630547B

公开(公告)日：2025-04-09

申请号：GB202412923

申请日：2023-03-21

Applicant: IBM

Inventor： MICHAEL KLEIN ,  PETRA LEBER ,  CEDRIC LICHTENAU ,  STEFAN PAYER ,  KERSTIN SCHELM

IPC: G06F7/483 ,  G06F7/499 ,  G06F7/74

Abstract: Rounding hexadecimal floating point numbers using binary incrementors, including: incrementing, by a first incrementor, a first subset of bits of an operand comprising a binary hexadecimal floating point operand; incrementing, by a second incrementor, a second subset of bits of the operand; generate an intermediate result based on a carryout of the second incrementor; and generate an incremented result based on a carryout of the first incrementor and one or more of: a first bit of the intermediate result or the carryout of the second incrementor.

公开(公告)号：GB2630547A

公开(公告)日：2024-11-27

申请号：GB202412923

申请日：2023-03-21

Applicant: IBM

Inventor： MICHAEL KLEIN ,  PETRA LEBER ,  CEDRIC LICHTENAU ,  STEFAN PAYER ,  KERSTIN SCHELM

IPC: G06F7/483 ,  G06F7/499 ,  G06F7/74

Abstract: Rounding hexadecimal floating point numbers using binary incrementors, including: incrementing, by a first incrementor, a first subset of bits of an operand comprising a binary hexadecimal floating point operand; incrementing, by a second incrementor, a second subset of bits of the operand; generate an intermediate result based on a carryout of the second incrementor; and generate an incremented result based on a carryout of the first incrementor and one or more of: a first bit of the intermediate result or the carryout of the second incrementor.

公开(公告)号：GB2632957A

公开(公告)日：2025-02-26

申请号：GB202416053

申请日：2023-01-17

Applicant: IBM

Inventor： ADAM COLLURA ,  MICHAEL ROMAIN ,  WILLIAM HUOTT ,  PAWEL OWCZARCZYK ,  CHRISTIAN JACOBI ,  ANTHONY SAPORITO ,  CHUNG-LUNG SHUM ,  ALPER BUYUKTOSUNOGLU ,  TOBIAS WEBEL ,  MICHAEL CADIGAN JR ,  PAUL LOGSDON ,  SEAN CAREY ,  KARL ANDERSON ,  MARK CICHANOWSKI ,  STEFAN PAYER

IPC: H02H9/04 ,  G05F1/571 ,  H02H3/20

Abstract: The method and systems described herein provide for identifying and mitigating undesirable power or voltage fluctuations in regions of a semiconductor device. The method includes detecting a region, such as an individual processor, of a processor chip exhibiting a reduced power draw and a resulting localized voltage spike (e.g., a spike that exceeds Vmax) that would accelerate overall device end-of-life. The described systems respond by activating circuits or current generators located in the given region to draw additional power via a protective current. The protective current lowers the local voltage spikes back to within some pre-specified range. The resulting reduction in the time above Vmax in testing reduces the number of devices that will need to be discarded due to Vmax violations as well as increases the expected reliability and lifespan of the device in operation.

公开(公告)号：GB2602405A

公开(公告)日：2022-06-29

申请号：GB202203285

申请日：2020-08-07

Applicant: IBM

Inventor： RAZVAN FIGULI ,  STEFAN PAYER ,  CEDRIC LICHTENAU ,  KERSTIN SCHELM

IPC: G06F11/07

Abstract: A method for detecting faults in substring search operations includes providing, using a processor unit including vector registers of M vector elements each, anMxM Matrix of comparators for characterwise comparison of the elements of a reference string stored in a first one of the vector registers and a target string stored in a second one of the vector registers. A vector element is an n-bit element for encoding a character.A resulting bit vector is generated using comparison performed by the MxM matrix. The resulting bit vector indicates characters of the target string that fully match the reference string and indicates characters of the target string that partially match the reference string. Fault detection in the substring search operations is performed by utilizing the resulting bit vector.