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公开(公告)号：GB2630547A
公开(公告)日：2024-11-27
申请号：GB202412923
申请日：2023-03-21
Applicant: IBM
Inventor： MICHAEL KLEIN , PETRA LEBER , CEDRIC LICHTENAU , STEFAN PAYER , KERSTIN SCHELM
Abstract: Rounding hexadecimal floating point numbers using binary incrementors, including: incrementing, by a first incrementor, a first subset of bits of an operand comprising a binary hexadecimal floating point operand; incrementing, by a second incrementor, a second subset of bits of the operand; generate an intermediate result based on a carryout of the second incrementor; and generate an incremented result based on a carryout of the first incrementor and one or more of: a first bit of the intermediate result or the carryout of the second incrementor.
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公开(公告)号：GB2595170A
公开(公告)日：2021-11-17
申请号：GB202111753
申请日：2020-01-23
Applicant: IBM
Inventor： CEDRIC LICHTENAU , JONATHAN BRADBURY , REID COPELAND , PETRA LEBER
IPC: G06F9/06
Abstract: In a technique for instruction interrupt suppression for an overflow condition, an instruction is executed, and a determination is made that an overflow condition occurred. Based on a per-instruction overflow interrupt indicator being set to a defined value, interrupt processing for the overflow condition is performed, and based on the per- instruction overflow interrupt indicator being set to another defined value, the interrupt processing for the overflow condition is bypassed.
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公开(公告)号：GB2530989B
公开(公告)日：2016-08-17
申请号：GB201417580
申请日：2014-10-06
Applicant: IBM
Inventor： CEDRIC LICHTENAU , SILVIA MELITTA MUELLER , PETRA LEBER , STEVEN R CARLOUGH , MICHAEL KROENER
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公开(公告)号：IL302916A
公开(公告)日：2023-07-01
申请号：IL30291623
申请日：2023-05-14
Applicant: IBM , ERIC MARK SCHWARZ , PETRA LEBER , KERSTIN CLAUDIA SCHELM , SILVIA MELITTA MUELLE , REID COPELAND , XIN GUO , CEDRIC LICHTENAU
Inventor： ERIC MARK SCHWARZ , PETRA LEBER , KERSTIN CLAUDIA SCHELM , SILVIA MELITTA MUELLE , REID COPELAND , XIN GUO , CEDRIC LICHTENAU
Abstract: An instruction to perform scaling, converting and splitting operations is executed. The executing the instruction includes scaling an input value in one format to provide a scaled result. The scaled result is converted from the one format to provide a converted result in another format. The converted result is split into multiple parts, and one or more parts of the multiple parts are placed in a selected location.
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公开(公告)号：GB2595191B
公开(公告)日：2022-09-21
申请号：GB202112124
申请日：2020-01-27
Applicant: IBM
Inventor： CEDRIC LICHTENAU , REID COPELAND , PETRA LEBER , JONATHAN BRADBURY , SILVIA MELITTA MUELLER , XIN GUO
Abstract: Digit validation check control for execution of an instruction. A process obtains an instruction to perform operation(s) using input value(s). The instruction includes a no validation indicator for controlling whether digit validation check control is enabled for execution of the instruction. The process executes the instruction, including determining, based on the no validation indicator, whether digit validation check control is enabled for execution of the instruction, and performing processing based on the determining. Based on the no validation indicator being set to a defined value, digit validation check control is enabled and the processing includes forcing a digit check error indicator output by the executing to indicate no digit check error with respect to the at least one input value.
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Patent Agency Ranking
公开(公告)号：GB2595191A
公开(公告)日：2021-11-17
申请号：GB202112124
申请日：2020-01-27
Applicant: IBM
Inventor： CEDRIC LICHTENAU , REID COPELAND , PETRA LEBER , JONATHAN BRADBURY , SILVIA MELITTA MUELLER , XIN GUO
IPC: G06F9/455
Abstract: Digit validation check control for execution of an instruction. A process obtains an instruction to perform operation(s) using input value(s). The instruction includes a no validation indicator for controlling whether digit validation check control is enabled for execution of the instruction. The process executes the instruction, including determining, based on the no validation indicator, whether digit validation check control is enabled for execution of the instruction, and performing processing based on the determining. Based on the no validation indicator being set to a defined value, digit validation check control is enabled and the processing includes forcing a digit check error indicator output by the executing to indicate no digit check error with respect to the at least one input value.
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公开(公告)号：GB2572719A
公开(公告)日：2019-10-09
申请号：GB201909646
申请日：2017-11-30
Applicant: IBM
Inventor： SILVIA MELITTA MUELLER , PETRA LEBER , CEDRIC LICHTENAU
Abstract: A circuit is provided which includes arithmetic computation logic (201) configured to add or subtract operands of variable length to produce a result in a sign-magnitude data format. The circuit also includes an overflow detector (210) to provide an overflow signal indicative of whether the result fits within a specified result length l. The overflow detector (210) operates on the operands prior to the arithmetic computation logic (201) producing the result to determine, independent of the result produced by the arithmetic computation logic (201), whether the result fits within the specified result length l.
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公开(公告)号：GB2530989A
公开(公告)日：2016-04-13
申请号：GB201417580
申请日：2014-10-06
Applicant: IBM
Inventor： CEDRIC LICHTENAU , SILVIA MELITTA MUELLER , PETRA LEBER , STEVEN R CARLOUGH , MICHAEL KROENER
Abstract: Floating point arithmetic logic (10) for rounding the final result of an arithmetic operation on a first number (104) and a second number (106) both in either binary floating point format or decimal floating point format. Binary floating point format numbers are mapped S10 to a decimal floating point format, by padding bits (18) to form digits in order to share the same fields as in a decimal floating point format. A guard digit (28) of zero (58) of at least one of the first or second numbers is generated S12 by transforming the first and second numbers (108; 110) using a compressing function (30) such as a carry-save adder. A result (130) and result plus one (132) are calculated depending on the arithmetic operation a sum (66), a first difference (67) or a second difference (68) of the transformed numbers (112, 114). Injection values (24, 26) for rounding a final result (20) are generated in dependence on the first and second numbers being in a decimal or binary floating point format, a rounding mode and of the arithmetic operation. Injection carry values (16, 17) are generated based on the transformed first and second floating point numbers and the injection values. The final result is selected from the result, the result plus one and a least significant digit (60) based on the injection carry values and end around carry signals.
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公开(公告)号：GB2630547B
公开(公告)日：2025-04-09
申请号：GB202412923
申请日：2023-03-21
Applicant: IBM
Inventor： MICHAEL KLEIN , PETRA LEBER , CEDRIC LICHTENAU , STEFAN PAYER , KERSTIN SCHELM
Abstract: Rounding hexadecimal floating point numbers using binary incrementors, including: incrementing, by a first incrementor, a first subset of bits of an operand comprising a binary hexadecimal floating point operand; incrementing, by a second incrementor, a second subset of bits of the operand; generate an intermediate result based on a carryout of the second incrementor; and generate an incremented result based on a carryout of the first incrementor and one or more of: a first bit of the intermediate result or the carryout of the second incrementor.
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公开(公告)号：GB2572719B
公开(公告)日：2020-05-20
申请号：GB201909646
申请日：2017-11-30
Applicant: IBM
Inventor： SILVIA MELITTA MUELLER , PETRA LEBER , CEDRIC LICHTENAU
Abstract: A circuit is provided which includes arithmetic computation logic configured to add or subtract operands of variable length to produce a result in a sign-magnitude data format. The circuit also includes an overflow detector to provide an overflow signal indicative of whether the result fits within a specified result length l. The overflow detector operates on the operands prior to the arithmetic computation logic producing the result to determine, independent of the result produced by the arithmetic computation logic, whether the result fits within the specified result length l.
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