公开(公告)号：DE69604810T2

公开(公告)日：2000-04-20

申请号：DE69604810

申请日：1996-08-09

Applicant: IBM

Inventor： LEAS JAMES ,  KOSS ROBERT ,  VAN HORN JODY ,  WALKER GEORGE ,  PERRY CHARLES ,  GARDELL DAVID ,  DINGLE STEVE ,  PRILIK RONALD

IPC: G01R1/06 ,  G01R1/073 ,  G01R31/28 ,  H01L21/66 ,  G01R31/316

Abstract: An apparatus and a method for simultaneously testing or burning in all the integrated circuit chips on a product wafer. The apparatus comprises a glass ceramic carrier having test chips and means for connection to pads of a large number of chips on a product wafer. Voltage regulators on the test chips provide an interface between a power supply and power pads on the product chips, at least one voltage regulator for each product chip. The voltage regulators provide a specified Vdd voltage to the product chips, whereby the Vdd voltage is substantially independent of current drawn by the product chips. The voltage regulators or other electronic means limit current to any product chip if it has a short. The voltage regulator circuit may be gated and variable and it may have sensor lines extending to the product chip. The test chips can also provide test functions such as test patterns and registers for storing test results.

公开(公告)号：DE69604810D1

公开(公告)日：1999-11-25

申请号：DE69604810

申请日：1996-08-09

Applicant: IBM

Inventor： LEAS JAMES ,  KOSS ROBERT ,  VAN HORN JODY ,  WALKER GEORGE ,  PERRY CHARLES ,  GARDELL DAVID ,  DINGLE STEVE ,  PRILIK RONALD

IPC: G01R1/06 ,  G01R1/073 ,  G01R31/28 ,  H01L21/66 ,  G01R31/316

Abstract: An apparatus and a method for simultaneously testing or burning in all the integrated circuit chips on a product wafer. The apparatus comprises a glass ceramic carrier having test chips and means for connection to pads of a large number of chips on a product wafer. Voltage regulators on the test chips provide an interface between a power supply and power pads on the product chips, at least one voltage regulator for each product chip. The voltage regulators provide a specified Vdd voltage to the product chips, whereby the Vdd voltage is substantially independent of current drawn by the product chips. The voltage regulators or other electronic means limit current to any product chip if it has a short. The voltage regulator circuit may be gated and variable and it may have sensor lines extending to the product chip. The test chips can also provide test functions such as test patterns and registers for storing test results.

公开(公告)号：AT438926T

公开(公告)日：2009-08-15

申请号：AT02796462

申请日：2002-08-29

Applicant: IBM

Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK ,  HOLMES STEVEN ,  HORAK DAVID ,  LEAS JAMES ,  MA WILLIAM ,  RABIDOUX PAUL

IPC: H01L29/76 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/60 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/78 ,  H01L29/786 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

Abstract: A method of manufacturing provides a vertical transistor particularly suitable for high density integration and which includes potentially independent gate structures on opposite sides of a semiconductor pillar formed by etching or epitaxial growth in a trench. The gate structure is surrounded by insulating material which is selectively etchable to isolation material surrounding the transistor. A contact is made to the lower end of the pillar (e.g. the transistor drain) by selectively etching the isolation material selective to the insulating material. The upper end of the pillar is covered by a cap and sidewalls of selectively etchable materials so that gate and source connection openings can also be made by selective etching with good registration tolerance. A dimension of the pillar in a direction parallel to the chip surface is defined by a distance between isolation regions and selective etching and height of the pillar is defined by thickness of a sacrificial layer.