公开(公告)号：DE69604810T2

公开(公告)日：2000-04-20

申请号：DE69604810

申请日：1996-08-09

Applicant: IBM

Inventor： LEAS JAMES ,  KOSS ROBERT ,  VAN HORN JODY ,  WALKER GEORGE ,  PERRY CHARLES ,  GARDELL DAVID ,  DINGLE STEVE ,  PRILIK RONALD

IPC: G01R1/06 ,  G01R1/073 ,  G01R31/28 ,  H01L21/66 ,  G01R31/316

Abstract: An apparatus and a method for simultaneously testing or burning in all the integrated circuit chips on a product wafer. The apparatus comprises a glass ceramic carrier having test chips and means for connection to pads of a large number of chips on a product wafer. Voltage regulators on the test chips provide an interface between a power supply and power pads on the product chips, at least one voltage regulator for each product chip. The voltage regulators provide a specified Vdd voltage to the product chips, whereby the Vdd voltage is substantially independent of current drawn by the product chips. The voltage regulators or other electronic means limit current to any product chip if it has a short. The voltage regulator circuit may be gated and variable and it may have sensor lines extending to the product chip. The test chips can also provide test functions such as test patterns and registers for storing test results.

公开(公告)号：GB2365622A

公开(公告)日：2002-02-20

申请号：GB0103577

申请日：2001-02-14

Applicant: IBM

Inventor： SAMBUCETTI CARLOS J ,  EDELSTEIN DANIEL C ,  GAUDIELLO JOHN G ,  RUBINO JUDITH M ,  WALKER GEORGE

IPC: H05K3/34 ,  C23C18/16 ,  H01L21/60 ,  H01L23/12 ,  H01L23/485 ,  H01L23/532 ,  H05K3/24 ,  H05K13/06

Abstract: A copper pad surface 14 of an IC chip is first prepared, e.g. cleaned by an acid solution, a protection layer 16 of a phosphorus or boron-containing metal alloy is then deposited on the copper pad surface, and then an adhesion layer 18 of a noble metal is deposited on top of the protection layer. The protection layer 16 may be a single layer, or two or more layers intimately joined together formed of a phosphorus or boron-containing metal alloy such as Ni-P, Co-P, Co- W-P, Co-Sn-P, Ni-W-P, Co-B, Ni-B, Co-Sn-B, Co-W-B and Ni-W-B. A suitable thickness for the protection layer is between about 1,000 Ñ and about 10,000 Ñ, and preferably between about 3,000 Ñ and about 7,000 Ñ. The adhesion layer 18 can be formed of a noble metal such as Au, Pt, Pd and Ag to a thickness between about 500 Ñ and about 4,000 Ñ, and preferably between about 1,000 Ñ and about 2,000 Ñ. A nucleation layer of Pd may be deposited between the copper conductive pad surface 14 and the protection layer 16 prior to the electroless deposition of the protection layer. An additional noble metal layer may be deposited on top of the adhesion layer 18 by an electroless Au deposition process to increase the thickness of the final noble metal layer to about 2,000 Ñ 12,000 Ñ, and preferably between about 4,000 Ñ and about 6,000 Ñ. The pad is suitable for a wireband or solder bump connection

公开(公告)号：DE69604810D1

公开(公告)日：1999-11-25

申请号：DE69604810

申请日：1996-08-09

Applicant: IBM

Inventor： LEAS JAMES ,  KOSS ROBERT ,  VAN HORN JODY ,  WALKER GEORGE ,  PERRY CHARLES ,  GARDELL DAVID ,  DINGLE STEVE ,  PRILIK RONALD

IPC: G01R1/06 ,  G01R1/073 ,  G01R31/28 ,  H01L21/66 ,  G01R31/316

Abstract: An apparatus and a method for simultaneously testing or burning in all the integrated circuit chips on a product wafer. The apparatus comprises a glass ceramic carrier having test chips and means for connection to pads of a large number of chips on a product wafer. Voltage regulators on the test chips provide an interface between a power supply and power pads on the product chips, at least one voltage regulator for each product chip. The voltage regulators provide a specified Vdd voltage to the product chips, whereby the Vdd voltage is substantially independent of current drawn by the product chips. The voltage regulators or other electronic means limit current to any product chip if it has a short. The voltage regulator circuit may be gated and variable and it may have sensor lines extending to the product chip. The test chips can also provide test functions such as test patterns and registers for storing test results.

公开(公告)号：AT522953T

公开(公告)日：2011-09-15

申请号：AT03770552

申请日：2003-09-30

Applicant: IBM

Inventor： VOLANT RICHARD ,  PETRARCA KEVIN ,  WALKER GEORGE

IPC: H01R12/00

Abstract: A three-dimensional package consisting of a plurality of folded integrated circuit chips ( 100, 110, 120 ) is described wherein at least one chip provides interconnect pathways for electrical connection to additional chips of the stack, and at least one chip ( 130 ) is provided with additional interconnect wiring to a substrate ( 500 ), package or printed circuit board. Further described, is a method of providing a flexible arrangement of interconnected chips that are folded over into a three-dimensional arrangements to consume less aerial space when mounted on a substrate, second-level package or printed circuit board.

公开(公告)号：MY119885A

公开(公告)日：2005-07-29

申请号：MYPI20010427

申请日：2001-01-31

Applicant: IBM

Inventor： SAMBUCETTI CARLOS J ,  EDELSTEIN DANIEL C ,  GAUDIELLO JOHN G ,  RUBINO JUDITH M ,  WALKER GEORGE

IPC: B32B15/00 ,  H05K3/34 ,  B05D5/12 ,  C23C18/16 ,  H01L21/60 ,  H01L23/12 ,  H01L23/485 ,  H01L23/532 ,  H05K3/24 ,  H05K13/06

Abstract: A METHOD FOR PREPARING A COPPER PAD SURFACE FOR ELECTRICAL CONNECTION THAT HAS SUPERIOR DIFFUSION BARRIER AND ADHESION PROPERTIES IS PROVIDED. IN THE METHOD, A COPPER PAD SURFACE (14) IS FIRST PROVIDED THAT HAS BEEN CLEANED BY AN ACID SOLUTION, A PROTECTION LAYER (16) OF A PHOSPHORUS OR BORON-CONTAINING METAL ALLOY IS THEN DEPOSITED ON THE COPPER PAD SURFACE, AND THEN AN ADHESION LAYER (18) OF A NOBLE METAL IS DEPOSITED ON TOP OF THE PROTECTION LAYER. THE PROTECTION LAYER MAY BE A SINGLE LAYER, OR TWO OR MORE LAYERS INTIMATELY JOINED TOGETHER FORMED OF A PHOSPHORUS OR BORON-CONTAINING METAL ALLOY SUCH AS NI-P, CO-P, CO-W-P, CO-SN-P, NI-W-P, CO-B, NI-B, CO-SN-B, CO-W-B AND NI-W-B TO A THICKNESS BETWEEN ABOUT 1,000 Å AND ABOUT 10,000 Å. THE ADHESION LAYER CAN BE FORMED OF A NOBLE METAL SUCH AS AU, PT, PD AND AG TO A THICKNESS BETWEEN ABOUT 500 Å AND ABOUT 4,000 Å.

公开(公告)号：GB2365622B

公开(公告)日：2004-08-11

申请号：GB0103577

申请日：2001-02-14

Applicant: IBM

Inventor： SAMBUCETTI CARLOS J ,  EDELSTEIN DANIEL C ,  GAUDIELLO JOHN G ,  RUBINO JUDITH M ,  WALKER GEORGE

IPC: H05K3/34 ,  C23C18/16 ,  H01L21/60 ,  H01L23/12 ,  H01L23/485 ,  H01L23/532 ,  H05K3/24 ,  H05K13/06

Abstract: A method for preparing a copper pad surface for electrical connection that has superior diffusion barrier and adhesion properties is provided. In the method, a copper pad surface is first provided that has been cleaned by an acid solution, a protection layer of a phosphorus or boron-containing metal alloy is then deposited on the copper pad surface, and then an adhesion layer of a noble metal is deposited on top of the protection layer. The protection layer may be a single layer, or two or more layers intimately joined together formed of a phosphorus or boron-containing metal alloy such as Ni-P, Co-P, Co-W-P, Co-Sn-P, Ni-W-P, Co-B, Ni-B, Co-Sn-B, Co-W-B and Ni-W-B to a thickness between about 1,000 Å and about 10,000 Å. The adhesion layer can be formed of a noble metal such as Au, Pt, Pd and Ag to a thickness between about 500 Å and about 4,000 Å.