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公开(公告)号：EP1226509A4
公开(公告)日：2007-09-26
申请号：EP00957269
申请日：2000-08-24
Applicant: IBM
Inventor： BASS BRIAN MITCHELL , CALVIGNAC JEAN-LOUIS , GALLO ANTHONY MATTEO , HEDDES MARCO C , LEAVENS ROSS BOYD , PATEL PIYUSH CHUNILAL , RINALDI MARK ANTHONY , SIEGEL MICHAEL STEVEN , VERPLANKEN FABRICE JEAN
CPC classification number: H04L49/602 , G06F15/80 , H04L49/351
Abstract: A network processor (10) useful in network switch apparatus and methods of operating such a processor in which data flow handling and flexibility is enhanced by the cooperation of an embedded processor complex (12) with a suite of peripherals (14-36 and 40), all formed on a common semiconductor substrate. The interface processors (16, 34) provide data path for inbound and outbound data flow and operate under the control of instructions stored in an instruction store formed on the semiconductor substrate, while storage of transiting data flow portions is provided by memory peripherals and interfaces to external memory elements.
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公开(公告)号：JP2001350638A
公开(公告)日：2001-12-21
申请号：JP2001104520
申请日：2001-04-03
Applicant: IBM
Inventor： DAVIS GORDON TAYLOR , HEDDES MARCO C , LEAVENS ROSS BOYD , VERPLANKEN FABRICE JEAN
Abstract: PROBLEM TO BE SOLVED: To attain the more efficient use of a processor resource. SOLUTION: When an execution is permitted in a thread that is stopping the acting, a prefetch buffer 118 is used in relation to a plurality of independent thread processings in a method as avoids an instantaneous stop. In order to realize the more efficient use of the processor resource, a mechanism 30 for controlling the switching from the thread within a processor to another thread is established. This mechanism imparts a temporary control to the alternative execution thread when a short waiting time event is generated, and imparts a perfect control to the alternative execution thread when a long waiting time even is generated. This thread control mechanism comprises a priority FIFO constituted so that the execution priorities of at least two execution threads within the processor are controlled according to their outputs on the basis of the length of the time when each execution thread is stayed within an FIFO 52.
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公开(公告)号：HU0203823A2
公开(公告)日：2003-05-28
申请号：HU0203823
申请日：2000-12-21
Applicant: IBM
Inventor： BASS BRIAN MITCHELL , CALVIGNAC JEAN LOUIS , DAVIS GORDON TAYLOR , GALLO ANTHONY MATTEO , HEDDES MARCO , JENKINS STEVEN KENNETH , LEAVENS ROSS BOYD , SIEGEL MICHAEL STEVEN , VERPLANKEN FABRICE JEAN
Abstract: A system and method of frame protocol classification and processing in a system for data processing (e.g., switching or routing data packets or frames). The present invention includes analyzing a portion of the frame according to predetermined tests, then storing key characteristics of the packet for use in subsequent processing of the frame. The key characteristics for the frame (or input information unit) include the type of layer 3 protocol used in the frame, the layer 2 encapsulation technique, the starting instruction address, flags indicating whether the frame uses a virtual local area network, and the identity of the data flow to which the frame belongs. Much of the analysis is preferably done using hardware so that it can be completed quickly and in a uniform time period. The stored characteristics of the frame are then used by the network processing complex in its processing of the frame. The processor is preconditioned with a starting instruction address and the location of the beginning of the layer 3 header as well as flags for the type of frame. That is, the instruction address or code entry point is used by the processor to start processing for a frame at the right place, based on the type of frame. Additional instruction addresses can be stacked and used sequentially at branches to avoid additional tests and branching instructions. Additionally, frames comprising a data flow can be processed and forwarded in the same order in which they are received.
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公开(公告)号：DE10110504B4
公开(公告)日：2006-11-23
申请号：DE10110504
申请日：2001-03-03
Applicant: IBM
Inventor： DAVIS GORDON TAYLOR , HEDDES MARCO C , LEAVENS ROSS BOYD , VERPLANKEN FRABRICE JEAN
Abstract: A mechanism controls a multi-thread processor so that when a first thread encounters a latency event for a first predefined time interval temporary control is transferred to an alternate execution thread for duration of the first predefined time interval and then back to the original thread. The mechanism grants full control to the alternate execution thread when a latency event for a second predefined time interval is encountered. The first predefined time interval is termed short latency event whereas the second time interval is termed long latency event.
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公开(公告)号：GB2366426A
公开(公告)日：2002-03-06
申请号：GB0108828
申请日：2001-04-09
Applicant: IBM
Inventor： DAVIS GORDON TAYLOR , HEDDES MARCO C , LEAVENS ROSS BOYD , RINALDI MARK A
Abstract: A processor system comprises a core language processor 101, co-processors 107 - 111; each having special purpose, scalar 116 and array 117, registers; and an interface between the processors, where the interface maps the special purpose registers into a common address map. The system may be utilised as a protocol processor unit to provide instruction communication to a network, and the co-processors may compute CRC checksums, move data between local and main memories, search a tree structure, enqueue packets or assist in accessing the contents of registers. The interface may take the form of an execution interface 106 or a data interface 130.
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Patent Agency Ranking
公开(公告)号：CA2385339C
公开(公告)日：2005-06-28
申请号：CA2385339
申请日：2000-12-21
Applicant: IBM
Inventor： JENKINS STEVEN KENNETH , SIEGEL MICHAEL STEVEN , CALVIGNAC JEAN LOUIS , BASS BRIAN MITCHELL , LEAVENS ROSS BOYD , VERPLANKEN FABRICE JEAN , HEDDES MARCO , DAVIS GORDON TAYLOR , GALLO ANTHONY MATTEO
Abstract: A system and method of frame protocol classification and processing in a system for data processing (e.g., switching or routing data packets or frames). The present invention includes analyzing a portion of the frame according to predetermined tests, then storing key characteristics of the packet for use in subsequent processing of the frame. The key characteristic s for the frame (or input information unit) include the type of layer 3 protoc ol used in the frame, the layer 2 encapsulation technique, the starting instruction address, flags indicating whether the frame uses a virtual local area network, and the identity of the data flow to which the frame belongs. Much of the analysis is preferably done using hardware so that it can be completed quickly and in a uniform time period. The stored characteristics o f the frame are then used by the network processing complex in its processing of the frame. The processor is preconditioned with a starting instruction addre ss and the location of the beginning of the layer 3 header as well as flags for the type of frame. That is, the instruction address or code entry point is used by the processor to start processing for a frame at the right place, based on the type of frame. Additional instruction addresses can be stacked and used sequentially at branches to avoid additional tests and branching instructions. Additionally, frames comprising a data flow can be processed a nd forwarded in the same order in which they are received.
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公开(公告)号：DE10110504A1
公开(公告)日：2001-10-18
申请号：DE10110504
申请日：2001-03-03
Applicant: IBM
Inventor： DAVIS GORDON TAYLOR , HEDDES MARCO C , LEAVENS ROSS BOYD , VERPLANKEN FRABRICE JEAN
Abstract: The method involves providing several instruction execution threads as independent processes in a sequential time frame. The execution threads are arranged in a queue so that they have overlapping access to the accessible data. A first thread in the queue is executed, and the execution control is transferred to the next thread in the queue when an event occurs that blocks the execution of the first thread. Independent claims are included for a processing system, a method of executing several independent threads in a processor, the use of a prefetch buffers in connection with a number of independent instruction threads, and for a thread execution controller.
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公开(公告)号：CA2385339A1
公开(公告)日：2001-07-12
申请号：CA2385339
申请日：2000-12-21
Applicant: IBM
Inventor： HEDDES MARCO , LEAVENS ROSS BOYD , SIEGEL MICHAEL STEVEN , GALLO ANTHONY MATTEO , DAVIS GORDON TAYLOR , BASS BRIAN MITCHELL , VERPLANKEN FABRICE JEAN , CALVIGNAC JEAN LOUIS , JENKINS STEVEN KENNETH
Abstract: A system and method of frame protocol classification and processing in a system for data processing (e.g., switching or routing data packets or frames). The present invention includes analyzing a portion of the frame according to predetermined tests, then storing key characteristics of the packet for use in subsequent processing of the frame. The key characteristic s for the frame (or input information unit) include the type of layer 3 protoc ol used in the frame, the layer 2 encapsulation technique, the starting instruction address, flags indicating whether the frame uses a virtual local area network, and the identity of the data flow to which the frame belongs. Much of the analysis is preferably done using hardware so that it can be completed quickly and in a uniform time period. The stored characteristics o f the frame are then used by the network processing complex in its processing of the frame. The processor is preconditioned with a starting instruction addre ss and the location of the beginning of the layer 3 header as well as flags for the type of frame. That is, the instruction address or code entry point is used by the processor to start processing for a frame at the right place, based on the type of frame. Additional instruction addresses can be stacked and used sequentially at branches to avoid additional tests and branching instructions. Additionally, frames comprising a data flow can be processed a nd forwarded in the same order in which they are received.
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公开(公告)号：AT280411T
公开(公告)日：2004-11-15
申请号：AT00983409
申请日：2000-12-21
Applicant: IBM
Inventor： BASS BRIAN MITCHELL , CALVIGNAC JEAN LOUIS , DAVIS GORDON TAYLOR , GALLO ANTHONY MATTEO , HEDDES MARCO , JENKINS STEVEN KENNETH , LEAVENS ROSS BOYD , SIEGEL MICHAEL STEVEN , VERPLANKEN FABRICE JEAN
Abstract: A system and method of frame protocol classification and processing in a system for data processing (e.g., switching or routing data packets or frames). The present invention includes analyzing a portion of the frame according to predetermined tests, then storing key characteristics of the packet for use in subsequent processing of the frame. The key characteristics for the frame (or input information unit) include the type of layer 3 protocol used in the frame, the layer 2 encapsulation technique, the starting instruction address, flags indicating whether the frame uses a virtual local area network, and the identity of the data flow to which the frame belongs. Much of the analysis is preferably done using hardware so that it can be completed quickly and in a uniform time period. The stored characteristics of the frame are then used by the network processing complex in its processing of the frame. The processor is preconditioned with a starting instruction address and the location of the beginning of the layer 3 header as well as flags for the type of frame. That is, the instruction address or code entry point is used by the processor to start processing for a frame at the right place, based on the type of frame. Additional instruction addresses can be stacked and used sequentially at branches to avoid additional tests and branching instructions. Additionally, frames comprising a data flow can be processed and forwarded in the same order in which they are received.
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公开(公告)号：CA2334393A1
公开(公告)日：2001-10-04
申请号：CA2334393
申请日：2001-02-02
Applicant: IBM
Inventor： DAVIS GORDON TAYLOR , VERPLANKEN FABRICE JEAN , LEAVENS ROSS BOYD , HEDDES MARCO C
Abstract: A prefetch buffer is used in connection with a plurality of independent thre ad processes in such a manner as to avoid an immediate stall when execution is given to an idle thread. A mechanism is established to control the switching from one thread to another within a Processor in order to achieve more efficient utilization of processor resources. This mechanism will grant temporary control to an alternate execution thread when a short latency even t is encountered, and will grant full control to an alternate execution thread when a long latency event is encountered. This thread control mechanism comprises a priority FIFO, which is configured such that its outputs control execution priority for two or more execution threads within a processor, based on the length of time each execution thread has been resident within the FIFO. The FIFO is loaded with an execution thread number each time a new task (a networking packet requiring classification and routing within a network) is dispatched for processing, where the execution thread number loaded into the FIFO corresponds to the thread number which is assigned to process the task. When a particular execution thread completes processing of a particular task, and enqueues the results for subsequent handling, the priority FIFO is further controlled toremove the corresponding execution thread number from the FIFO. When an active execution thread encounters a lo ng latency event, the corresponding thread number within the FIFO is removed from a high priority position in the FIFO, and placed into the lowest priority position of the FIFO. This thread control mechanism also comprises a Thread Control State Machine for each execution thread supported by the processor. The Thread Control State Machine further comprises four states. A n Init state is used while an execution thread is waiting for a task to process. Once a task is enqueued for processing, a Ready state is used to request execution cycles. Once access to the processor is granted, an Execute state is used to support actual processor execution. Requests for additional processor cycles are made from both the Ready state and the Execute state. The state machine is returned to the Init state once processing has been completed for the assigned task. A Wait state is used to suspend requests for execution cycles while the execution thread is stalled due to either a long-latency event or a short-latency event. This thread control mechanism further comprises an arbiter which uses thread numbers from the priority FIFO to determine which execution thread should be granted access to processor resources. The arbiter further process es requests for execution control from each execution thread, and selects one execution thre ad to be granted access to processor resources for each processor execution cycle by matching thread numbers from requesting execution threads with corresponding thread numbers in the priori ty FIFO.
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