中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

14 records (took 0.02 seconds)

    DEVICE AND METHOD FOR PERFORMING SHIFT/ROTATE OPERATIONS
    1.
    发明申请
    DEVICE AND METHOD FOR PERFORMING SHIFT/ROTATE OPERATIONS 审中-公开
    用于执行移位/旋转操作的装置和方法

    公开(公告)号：WO2004044731A3

    公开(公告)日：2004-12-16

    申请号：PCT/EP0350754

    申请日：2003-10-24

    Applicant: IBM ,  IBM DEUTSCHLAND ,  BUETTNER STEFAN ,  LEENSTRA JENS ,  MAEDING NICOLAS ,  PILLE JUERGEN

    Inventor： BUETTNER STEFAN ,  LEENSTRA JENS ,  MAEDING NICOLAS ,  PILLE JUERGEN

    IPC: G06F5/01 ,  G06F7/76

    CPC classification number: G06F7/762 ,  G06F5/01 ,  G06F5/015 ,  G06F2207/382 ,  G06F2207/3828

    Abstract: A method and device is provided for performing rotate operations on operands having a size of 2N bits, alternatively, for performing rotate operations on two operands each having a size of N bits to the left, whereby N is an integer. The device includes a control unit being adapted for exchanging M least significant bits of the output of a first rotate circuit with M least significant bits of the output of a second rotate circuit, when M =N is true, whenever an input having the width of 2N is to be rotated by M bits. For rotator arrays rotating N bit wide data to the right, it functions correspondingly.

    Abstract translation: 提供了一种方法和装置，用于对大小为2N位的操作数执行旋转操作，或者用于对两个操作数执行旋转操作，每个操作数具有N位的大小，其中N是整数。 该设备包括控制单元，该控制单元适于在M

    Schnelle Prädikattabellensuchen unter Verwendung einer Architektur mit einer Einzelanweisung und mehrfachen Daten
    4.
    发明专利
    Schnelle Prädikattabellensuchen unter Verwendung einer Architektur mit einer Einzelanweisung und mehrfachen Daten 未知

    公开(公告)号：DE102013204515A1

    公开(公告)日：2013-10-02

    申请号：DE102013204515

    申请日：2013-03-15

    Applicant: IBM

    Inventor： DINER EDUARD ,  LEENSTRA JENS ,  RAMAN VIJAYSHANKAR ,  STORM ADAM J

    IPC: G06F17/30

    Abstract: Bereitgestellt wird ein Ansatz, bei dem ein Prozessor eine Suchanforderung zum Suchen von in einer Datentabelle enthaltenen Daten empfängt. Der Prozessor wählt eine Spalte in der Datentabelle aus, die der Suchanforderung entspricht, und ruft Spaltendateneinträge aus der ausgewählten Spalte ab. Außerdem ermittelt der Prozessor die Breite der ausgewählten Spalte und wählt einen Suchalgorithmus auf der Grundlage der ermittelten Spaltenbreite aus. Danach lädt der Prozessor die Spaltendateneinträge in Spaltendatenvektoren und berechnet Suchergebnisse aus den Spaltendatenvektoren unter Verwendung des ausgewählten Suchalgorithmus.

    7.
    发明专利
    未知

    公开(公告)号：DE10110576B4

    公开(公告)日：2008-06-12

    申请号：DE10110576

    申请日：2001-03-06

    Applicant: IBM

    Inventor： HOFSTEE PETER ,  LEENSTRA JENS ,  TAST HANS-WERNER ,  WENDEL DIETER

    IPC: G06F11/26 ,  G01R31/3185

    Abstract: The present invention relates to improvements concerning logic and timing verification as the testability of a hardware circuit comprising embeddings of dynamic logic circuits in a static environment. The clocked macros comprising the dynamic logic circuit are bounded at both input and output by latches, keeping input and output signals to the clocked macro static. The static input signals are processed with wave formatting means in order to generate a wave form usable for an evaluation by the dynamic logic circuit, and the dynamic logic output signal is converted back to a static signal by a set/reset latch such that it can be latched by the clock signal of the static embedding circuit. Thus, the analysis methods for timing and logic simulation during chip design can be the same as those used for static logic and, in particular, the LSSD testing methods can be used.

    8.
    发明专利
    未知

    公开(公告)号：DE10110578B4

    公开(公告)日：2004-06-03

    申请号：DE10110578

    申请日：2001-03-06

    Applicant: IBM

    Inventor： LEENSTRA JENS ,  MUELLER ANTJE ,  PILLE JUERGEN ,  WENDEL DIETER

    IPC: G06F13/18 ,  G06F13/26 ,  G06F7/00

    Abstract: A storage device and a method for determining the entry with the highest priority in a buffer memory. The method is characterized by the steps of operating a plurality of priority subfilter circuits each of them covering a disjunct subgroup of the total of entries and each selecting the entry with the highest subgroup priority, and selecting the entry associated with the highest priority subgroup. The storage device is able to be allocated and deallocated repeatedly during processing program instructions in a computer system. The storage device is further characterized by an operator for operating a plurality of priority subfilter circuits. Each of priority subfilter circuits covers a disjunct subgroup of the total of entries and each selecting the entry with the highest subgroup priority. The storage device is still further characterized by a selector for selecting the entry associated with the highest priority subgroup.

Patent Agency Ranking