公开(公告)号：DE19910451C2

公开(公告)日：2003-08-14

申请号：DE19910451

申请日：1999-03-10

Applicant: IBM

Inventor： DAO TRONG SON ,  LEBER PETRA ,  LEENSTRA JENS

IPC: G06F9/38 ,  G06F15/163

公开(公告)号：DE19910451A1

公开(公告)日：1999-11-04

申请号：DE19910451

申请日：1999-03-10

Applicant: IBM

Inventor： DAO TRONG SON ,  LEBER PETRA ,  LEENSTRA JENS

IPC: G06F9/38 ,  G06F15/163

Abstract: The single chip multiprocessor has 2 symmetrical processors (101,102) and a common execution unit, utilized by each of the processors, with transfer of data from each of the processors to the common execution unit in successive clock cycles. An Independent claim for a manufacturing method for a multiprocessor is also included.

公开(公告)号：DE10056764B4

公开(公告)日：2007-09-06

申请号：DE10056764

申请日：2000-11-11

Applicant: IBM

Inventor： DAO TRONG SON ,  SAUER WOLFRAM ,  TAST HANS-WERNER

IPC: G06F12/02 ,  G06F9/38

公开(公告)号：DE10056764A1

公开(公告)日：2001-06-28

申请号：DE10056764

申请日：2000-11-11

Applicant: IBM

Inventor： DAO TRONG SON ,  SAUER WOLFRAM ,  TAST HANS-WERNER

IPC: G06F9/38 ,  G06F12/02

Abstract: Storage capacity is provided in a memory according to memory requirement. Additional storage space is provided for additional storage capacity in order to accommodate additional memory requirement. Independent claims are also included for the following: (a) a memory device for computer system; (b) a sub-unit for utilization in microprocessor device; (c) a microprocessor with one sub-unit; (d) a computer system with microprocessor device; (e) a computer program adapted for memory device utilization efficiency improving method; (f) and a computer program product stored on medium useful for computer.

公开(公告)号：DE19614480C2

公开(公告)日：2000-09-07

申请号：DE19614480

申请日：1996-04-12

Applicant: IBM

Inventor： GERWIG GUENTER ,  DAO TRONG SON ,  GETZLAFF KLAUS ,  HALLER WILHELM

IPC: G06F7/485 ,  G06F7/00 ,  G06F7/50 ,  G06F7/507 ,  G06F7/74

Abstract: PCT No. PCT/EP95/01455 Sec. 371 Date May 13, 1997 Sec. 102(e) Date May 13, 1997 PCT Filed Apr. 18, 1995 PCT Pub. No. WO96/33456 PCT Pub. Date Oct. 24, 1996A method and apparatus for the determination of leading zero digits of a sum is presented herein. The technique incorporates the parallel determination of partial sums of single digits accounting for the possibility of carries and on the basis thereof the pre-determination of potential zero digits or potential leading zero digits. Upon the establishment of a correct partial sum, the potential zero digits are selected and evaluated thereby determining the leading zero digits. The invention may be implemented in an adder in parallel or via a hierarchical structure. The parallelism permits time-savings in the determination of a normalized sum. The invention is preferably incorporated into adders, floating point computing units and/or data processing units.