公开(公告)号：JP2005333143A

公开(公告)日：2005-12-02

申请号：JP2005147449

申请日：2005-05-20

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BELYANSKY MICHAEL P ,  LIU JOYCE C ,  WANN HSING JEN ,  RICHARD STEPHAN WEISS

IPC: H01L21/316 ,  H01L21/336 ,  H01L21/4763 ,  H01L27/088 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

Abstract: PROBLEM TO BE SOLVED: To provide improved technology for forming high speed logical gate of a semiconductor device.
SOLUTION: An FET (field effect transistor) has: a gate disposed between a source and a drain; a gate dielectric layer disposed under the gate; and spacers disposed on the sides of the gate. The gate dielectric layer is made of a conventional oxide, and the spacer has a reduced dielectric constant (k). The reduced dielectric constant (k) can be made smaller than 3.85, and can be made larger than 3.85 (approximately same as that of the oxide) and smaller than 7.0 (approximately same as that of nitride). The spacer consists preferably of a material which can be etched selectively in relation to the gate dielectric layer. The spacer can have porosity, and a thin layer which prevents moisture absorption is deposited on a surface of the porous spacer. The spacer can be made of a material which is chosen from the group consisting of Black Diamond, Coral, TERA and a Blok type material. A hole is formed into the material of the spacer by exposing the spacer to oxygen plasma.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供用于形成半导体器件的高速逻辑门的改进技术。 解决方案：FET（场效应晶体管）具有：设置在源极和漏极之间的栅极; 设置在栅极下方的栅介质层; 以及设置在门的侧面上的间隔物。 栅极电介质层由常规氧化物制成，间隔物具有降低的介电常数（k）。 降低的介电常数（k）可以小于3.85，并且可以大于3.85（大致与氧化物相同）且小于7.0（与氮化物大致相同）。 间隔件优选地由可以相对于栅极介电层选择性蚀刻的材料构成。 间隔物可以具有多孔性，并且防止吸湿的薄层沉积在多孔隔离物的表面上。 间隔物可以由选自黑钻石，珊瑚，TERA和Blok型材料的材料制成。 通过将间隔物暴露于氧等离子体中，在隔离物的材料中形成孔。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：WO03015132A9

公开(公告)日：2004-02-19

申请号：PCT/EP0208784

申请日：2002-08-06

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： DOBUZINSKY DAVID MARK ,  KHAN BABAR ALI ,  LIU JOYCE C ,  WENSLEY PAUL ,  YU CHIENFAN

IPC: H01L21/3213 ,  H01L21/60 ,  H01L21/8234 ,  H01L21/8242

CPC classification number: H01L27/10894 ,  H01L21/32139 ,  H01L21/76897 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/10873

Abstract: A method of fabricating an integrated circuit chip having a first region of a first layout rule and a second region of a second layout rule. The method includes using a first material to establish a first hard mask pattern in only the first region and using a second material to establish a second hard mask pattern on top of the first hard mask pattern. The second material is additionally used to establish a third hard mask pattern in the second region.

Abstract translation: 一种制造具有第一布局规则的第一区域和第二布局规则的第二区域的集成电路芯片的方法。 该方法包括使用第一材料仅在第一区域中建立第一硬掩模图案，并且使用第二材料在第一硬掩模图案的顶部上建立第二硬掩模图案。 第二材料另外用于在第二区域中建立第三硬掩模图案。

公开(公告)号：GB2368457A

公开(公告)日：2002-05-01

申请号：GB0108448

申请日：2001-04-03

Applicant: IBM

Inventor： DALTON TIMOTHY JOSEPH ,  JAHNES CHRISTOPHER V ,  LIU JOYCE C ,  PURUSHOTHAMAN SAMPATH

IPC: H01L21/28 ,  H01L21/316 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/52

Abstract: A permanent protective hardmask 40 protects the dielectric properties of a main bulk dielectric layer 30 having a desirably low dielectric constant in a semiconductor device from undesirable increases in the dielectric constant, undesirable increases in current leakage, and low device yield from surface scratching during subsequent processing steps. The protective hardmask 40 further includes a single layer 50 or dual layer 50,60 sacrificial hardmask particularly useful when interconnect structures such as via openings and/or lines are formed in the low dielectric material during the course of making the final product. The sacrificial hardmask layers 50,60 and the permanent hardmask layer 40 may be formed in a single step from a same precursor wherein process conditions are altered to provide films of differing dielectric constants. Most preferably, a dual damascene structure has a tri-layer hardmask comprising silicon carbide, PECVD silicon nitride, and PECVD silicon dioxide, respectively, formed over a bulk low dielectric constant interlevel dielectric prior to forming the interconnect structures in the interlevel dielectric. The protective hardmask 40 has a low dielectric constant k which may be the same or similar to that of the bulk dielectric layer 30.

公开(公告)号：GB2345790B

公开(公告)日：2003-12-10

申请号：GB9927378

申请日：1999-11-22

Applicant: IBM

Inventor： MCGAHAY VINCENT JAMES ,  IVERS THOMAS HENRY ,  NYE HENRY ,  LIU JOYCE C

IPC: H01L21/3205 ,  H01L21/28 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532

Abstract: Poorly adherent layers such as silicon nitride and silicon dioxide exhibit improved adhesion to copper member by providing an intervening germanium-containing layer. The germanium-containing layer is copper germanide, germanium oxide, germanium nitride or combinations thereof. The germanium-containing layer enhances the adhesion such that the poorly adherent layer is less susceptible to delamination from the copper member.