公开(公告)号：EP1371091A4

公开(公告)日：2009-04-01

申请号：EP01990800

申请日：2001-12-04

Applicant: IBM

Inventor： GATES STEPHEN MCCONNELL ,  HEDRICK JEFFREY CURTIS ,  NITTA SATYANARAYANA V ,  PURUSHOTHAMAN SAMPATH ,  TYBERG CHRISTY SENSENICH

IPC: H01L23/48 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76835 ,  H01L21/76811 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A low-k dielectric metal conductor interconnect structure having no micro-trenches present therein and a method of forming such a structure are provided. The control over the conductor resistance is obtained using a buried etch stop layer (56) having a second atomic composition located between the line and via dielectric layers (54', 58') of porous low-k dielectrics having a first atomic composition. The inventive interconnect structure also includes a hard mask (60) which assists in forming the interconnect structure of the dual damascene-type. The first and second composition are selected to obtain etch selectivity of at least 10 to 1 or higher, and are selected from specific groups of porous low-k organic or inorganic materials with specific atomic compositions and other discoverable quantities.

公开(公告)号：EP2235744A4

公开(公告)日：2011-12-14

申请号：EP09704513

申请日：2009-01-15

Applicant: IBM

Inventor： CLEVENGER LAWRENCE A ,  DORIS BRUCE B ,  HUANG ELBERT E ,  PURUSHOTHAMAN SAMPATH ,  RADENS CARL J

IPC: H01L29/78 ,  H01L21/311 ,  H01L21/336 ,  H01L21/8238

CPC classification number: H01L21/31144 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7843

公开(公告)号：EP1371090A4

公开(公告)日：2007-10-24

申请号：EP01990106

申请日：2001-12-10

Applicant: IBM

Inventor： GATES STEPHEN MCCONNELL ,  HEDRICK JEFFREY CURTIS ,  NITTA SATYANARAYANA V ,  PURUSHOTHAMAN SAMPATH ,  TYBERG CHRISTY SENSENICH

IPC: H01L21/312 ,  H01L21/768 ,  H01L23/522 ,  H01L21/4763 ,  H01L23/48

CPC classification number: H01L21/76835 ,  H01L21/02118 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02282 ,  H01L21/3124 ,  H01L21/76811

Abstract: A metal wiring plus low-k dielectric interconnect structure of the dual damascene-type is provided wherein the conductive metal lines and vias are built into a hybrid low-k dielectric which includes two spun-on dielectrics that have different atomic compositions and at least one of the two spun-on dielectrics is porous. The two spun-on dielectrics used in forming the inventive hybrid low-k dielectric each have a dielectric constant of about 2.6 or less, preferably each dielectric of the hybrid structure has a k of from about 1.2 to about 2.2. By utilizing the inventive hybrid low-k dielectric excellent control over metal line resistance (trench depth) is obtained, without no added cost. This is achieved without the use of a buried etch stop layer, which if present, would be formed between the two spun-on dielectrics. Moreover, the spun-on dielectrics of the hybrid low-k dielectric have distinctly different atomic compositions enabling control over the conductor resistance using the bottom spun-on dielectric (i.e., via dielectric) as an inherent etch stop layer for the upper spun-on dielectric (i.e., line dielectric).

公开(公告)号：WO2005122195A3

公开(公告)日：2006-06-22

申请号：PCT/US2005018196

申请日：2005-05-23

Applicant: IBM ,  HUANG ELBERT E ,  KIM HYUNGJUN ,  MILLER ROBERT D ,  NITTA SATYANARAYANA V ,  PURUSHOTHAMAN SAMPATH

Inventor： HUANG ELBERT E ,  KIM HYUNGJUN ,  MILLER ROBERT D ,  NITTA SATYANARAYANA V ,  PURUSHOTHAMAN SAMPATH

IPC: H01L21/302 ,  H01G13/00 ,  H01L21/311 ,  H01L21/312 ,  H01L21/314 ,  H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76808 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/02282 ,  H01L21/3121 ,  H01L21/3125 ,  H01L21/3141 ,  H01L21/31608 ,  H01L21/31629 ,  H01L21/31695 ,  H01L21/76814 ,  H01L21/76834 ,  H01L21/76837 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Interconnect structures are fabricated by methods that comprise depositing a thin conformal passivation dielectric and/or diffusion barrier cap and/or hard mask by an atomic layer deposition or supercritical fluid based process.

Abstract translation: 通过包括通过原子层沉积或基于超临界流体的方法沉积薄的共形钝化介质和/或扩散阻挡盖和/或硬掩模的方法来制造互连结构。

公开(公告)号：JP2001291425A

公开(公告)日：2001-10-19

申请号：JP2001044645

申请日：2001-02-21

Applicant: IBM

Inventor： GELORME JEFFREY D ,  GANG SUN K ,  PAPATHOMAS KONSTANTINOS ,  PURUSHOTHAMAN SAMPATH

IPC: C09J9/02 ,  C09J163/00 ,  C09J171/10 ,  C09J191/00 ,  C09J201/00 ,  H01B1/00 ,  H01B1/22 ,  H01B13/00 ,  H01B17/64

Abstract: PROBLEM TO BE SOLVED: To provide a conductive adhesive having a wide property selective range by using micrometer size range particles of random size coated with a low-melting-point metal. SOLUTION: The coated particles are suspended in a vehicle consisting of a mixture of a thermosetting resin and a fusing agent resin selected for electrical and mechanical property in terms of viscosity, low contraction, screen printing ability and wide range specifications. The vehicle or resin system includes thermosetting alicyclic epoxy, thermosetting phenoxy polymer and thermosetting single-functional limonene oxide. A low-melting-point coating system for the particles contains In, Sn and In-Sn, Sn-Pb, Bi-Sn-In or InAg alloy. The micrometer size range particles contain Cu, Ni, Co, Ag, Pd, Pt, a polymer and a ceramic.

公开(公告)号：JPH11271773A

公开(公告)日：1999-10-08

申请号：JP3831799

申请日：1999-02-17

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレイション

Inventor： ALESSANDRO CESARE CAREGARI ,  PRAVEEN CHAUDARI ,  DOYLE JAMES P ,  JAMES ANDREW LACEY ,  SHUI CHIN ALAN LIEN ,  PURUSHOTHAMAN SAMPATH ,  MAHESHU GOVIND SAMANT ,  JAMES L SPADEL ,  JOACHIM SUTOA

IPC: G02F1/1337

CPC classification number: G02F1/13378 ,  G02F1/133734 ,  G02F2001/133765

Abstract: PROBLEM TO BE SOLVED: To obtain a low-cost, reliable light crystal display which is manufactured in a small number of steps by depositing an amorphous alignment layer on a transparent substrate by using a dry machining method. SOLUTION: The amorphous alignment layer is deposited on the transparent substrate by using the dry machining method such as plasma-reinforced chemical vapor-phase deposition. Then the atomic structure of the dry-machined alignment layer is aligned to at least one desired direction by using a particle beam device 48. A plasma generation unit 52 operates to generate ions and a group of three electrodes 54, 56, and 58 takes ions out to irradiate the substrate 20. The substrate 20 is fixed to a plate fixation platform 62 so that an angle θ as an angle of incidence of accelerated particles to a line perpendicular to the substrate 20 is maintained. The angle θ is preferably in a range of about 20 to 80 deg.. The alignment layer may be formed by a nonaqueous gas environmental deposition method such as vapor deposition, sputter deposition, and ion beam deposition.

Abstract translation: 要解决的问题：为了获得通过使用干式加工方法在透明基板上沉积非晶取向层而以少量步骤制造的低成本，可靠的光晶体显示器。 解决方案：通过使用等离子体增强化学气相沉积等干式加工方法将非晶取向层沉积在透明基板上。 然后通过使用粒子束装置48将干法加工的取向层的原子结构与至少一个所需的方向对准。等离子体产生单元52操作以产生离子，并且一组三个电极54,56和58取离子 从而照射基板20.基板20被固定到板固定平台62上，从而保持作为加速颗粒到垂直于基板20的线的入射角的角度θ。 角度θ优选在约20〜80度的范围内。取向层可以通过非水气体环境沉积方法形成，例如气相沉积，溅射沉积和离子束沉积。

公开(公告)号：JP2003218177A

公开(公告)日：2003-07-31

申请号：JP2003008636

申请日：2003-01-16

Applicant: IBM

Inventor： MAGERLEIN JOHN HAROLD ,  MCKNIGHT SAMUEL ROY ,  PETRARCA KEVIN SHAWN ,  PURUSHOTHAMAN SAMPATH ,  SAMBUCETTI CARLOS JUAN ,  VAN HORN JOSEPH J ,  VOLANT RICHARD PAUL ,  WALKER GEORGE FREDERICK

IPC: G01R31/26 ,  G01R1/04 ,  H01L21/60 ,  H01L21/66 ,  H05K3/24 ,  H05K3/32

Abstract: PROBLEM TO BE SOLVED: To provide an ability to test and 'burn in' device chips that require ultra high pitch I/O pads. SOLUTION: A system for testing a collection of the device chips by temporarily attaching them to a carrier having a plurality of receptacles with microdendritic features; the receptacles matching with and pushed in contact with a matching set of contact pads on the device chips; the carrier additionally having test pads connected to the receptacles through interconnect wiring. The system allows connecting the chips together and testing the collection as a whole by probing the test pads on the carrier. Burn-in of the collection of chips can also be performed on the temporary carrier, which is reusable. COPYRIGHT: (C)2003,JPO

公开(公告)号：JP2002270612A

公开(公告)日：2002-09-20

申请号：JP2002037664

申请日：2002-02-15

Applicant: IBM

Inventor： FORNOF ANN RHEA-HELENE ,  GATES STEPHEN MCCONNELL ,  HEDRICK JEFFREY CURTIS ,  NITTA SATYANARAYANA V ,  PURUSHOTHAMAN SAMPATH ,  TYBERG CHRISTY SENSENICH

IPC: H01L21/3205 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/316 ,  H01L21/768

Abstract: PROBLEM TO BE SOLVED: To provide a simple method where cost effect for patterning a mutual connection structure, in which the material subjected to spin-on is used as a hard mask, is high. SOLUTION: By using the material subjected to spin-on processing to the hard mask, a process can be executed by using a single tool, and usage of a single curing step is enhance, which is not normally used in a patterning process of the conventional technique, in which a CVD hard mask is used. Selection of a polishing stop layer (formed on a surface of low k dielectrics), which has permittivity nearly equal to that of dielectrics positioned below is enabled by using spin coating, so that effective permittivity of an obtained structure is not significantly increased. The hard mask used contains, at least two kinds of spin-on dielectric materials having different etching speeds.

公开(公告)号：JP2001351976A

公开(公告)日：2001-12-21

申请号：JP2001117668

申请日：2001-04-17

Applicant: IBM

Inventor： DALTON TIMOTHY J ,  CHRISTOPHER V JARNES ,  JOYCE C RYUU ,  PURUSHOTHAMAN SAMPATH

IPC: H01L21/28 ,  H01L21/316 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: PROBLEM TO BE SOLVED: To provide a permanent protection hard mask for protecting the dielectric characteristics of a main dielectric layer that has undesired low permittivity of a semiconductor device due to undesired increase in permittivity, undesired increase in current leakage, and a low device yield caused by surface scratch, when a continuous treatment processing is conducted. SOLUTION: This protection hard mask has a one- or two-layer sacrificial hard mask that is especially effective, when interconnection structure such as a via opening and/or a line is formed between low-permittivity materials, while a final product is manufacture. The sacrificial and permanent hard masks are formed of the same precursor substance in a single process, where process conditions are changed for giving a film having different permittivity. Most preferably, dual damascene structure has three-layer hard masks 40, 50, and 60 that are formed on the inter-level dielectric with bulk low permittivity, before the interconnection structure of the inter-level dielectric is formed.

公开(公告)号：JPH10270712A

公开(公告)日：1998-10-09

申请号：JP7620198

申请日：1998-03-24

Applicant: IBM

Inventor： CHRISTOS DIMITRIOS DIMITRACOPO ,  PETER RICHARD DANKOOMU ,  BRUCE K FARMAN ,  ROBERT B LEIBOWITZ ,  DEBORAH AN NOUMAYER ,  PURUSHOTHAMAN SAMPATH

IPC: H01L29/786 ,  H01L21/336 ,  H01L51/00 ,  H01L51/05

Abstract: PROBLEM TO BE SOLVED: To allow a combination of an organic semiconductor and an inorganic gate insulation layer with a high dielectric constant by combining a thin film gate insulator with a high dielectric constant, an organic semiconductor, a metal, a conductive polymer, and a heavily doped and highly conductive material. SOLUTION: A thin film gate insulator with a high dielectric constant such as a barium strontium titanate, an organic semiconductor such as pentasene, a metal, a conductive polymer, a heavily doped and highly conductive material as gate, source, and drain electrodes, and their combination are used to form a thin film transistor. In the structure thereof, an inorganic gate insulator with a high permittivity is used together with an organic insulator such as pentasene. The insulator with a high dielectric ε is annealed at 400 deg.C and the dielectric constant of ε>=15 can be realized. Therefore, a substrate made of glass or plastic can be used. The gate electrode can be formed of heavily doped silicon substrate as a gate.