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    System and method for tod clock steering
    1.
    发明专利
    System and method for tod clock steering 有权
    用于时间转向的系统和方法

    公开(公告)号：JP2007080264A

    公开(公告)日：2007-03-29

    申请号：JP2006243549

    申请日：2006-09-08

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： RONALD M SMITH SR ,  MARK S FARRELL ,  ENGLER EBERHARD ,  MEISSNER KLAUS

    IPC: G06F1/14

    CPC classification number: G06F1/14

    Abstract: PROBLEM TO BE SOLVED: To provide a system, a method and a computer program for steering a time-of-day (TOD) clock for a computer system having a physical clock providing a time base for executing operations that is stepped to a common oscillator. SOLUTION: The method includes computing a TOD clock offset value (d) to be added to a physical clock value (Tr) to obtain a logical TOD clock value (Tb), where the logical TOD clock value is adjustable without adjusting a stepping rate of the oscillator. COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种用于为具有物理时钟提供时间基准的计算机系统的时间（TOD）时钟的系统，方法和计算机程序，所述物理时钟提供用于执行步进到 一个共同的振荡器。 解决方案：该方法包括计算要添加到物理时钟值（Tr）的TOD时钟偏移值（d）以获得逻辑TOD时钟值（Tb），其中逻辑TOD时钟值可调整而不调整 振荡器的步进率。 版权所有（C）2007，JPO＆INPIT

    METHOD FOR ENSURING PRESENT OF LINE IN INSTRUCTION CACHE
    2.
    发明专利
    METHOD FOR ENSURING PRESENT OF LINE IN INSTRUCTION CACHE 审中-公开

    公开(公告)号：JP2003216490A

    公开(公告)日：2003-07-31

    申请号：JP2002371417

    申请日：2002-12-24

    Applicant: IBM

    Inventor： LIPTAY LYNNE M ,  MARK A CHECK ,  MARK S FARRELL ,  GIAMEI BRUCE C ,  CHARLES F WEBB

    IPC: G06F9/30 ,  G06F9/318 ,  G06F9/32 ,  G06F9/38 ,  G06F12/08 ,  G06F12/12

    Abstract: PROBLEM TO BE SOLVED: To provide a method for ensuring that a line is present in an instruction cache by instructing a computing system. SOLUTION: In the method for ensuring that the line is present in the instruction cache by instructing the computing system, a line-touch instruction is selected, the line-touch instruction is recognized as one type of a branch instruction which does not branch, the line-touch instruction is executed to fetch a target line from a target address into the instruction cache, and execution of the line-touch instruction is interlocked by completion of the fetch of the target line for preventing execution of an instruction following the line-touch instruction until the target line reaches the cache. COPYRIGHT: (C)2003,JPO

    METHOD FOR SETTING CONDITION AND CONDUCTING TEST BY SPECIAL MILLICODE INSTRUCTION
    3.
    发明专利
    METHOD FOR SETTING CONDITION AND CONDUCTING TEST BY SPECIAL MILLICODE INSTRUCTION 失效

    公开(公告)号：JP2000137611A

    公开(公告)日：2000-05-16

    申请号：JP9929599

    申请日：1999-04-06

    Applicant: IBM

    Inventor： CHARLES F WEBB ,  MARK S FARRELL

    IPC: G06F9/22 ,  G06F9/28 ,  G06F9/30 ,  G06F9/302 ,  G06F9/308 ,  G06F9/318 ,  G06F9/32

    Abstract: PROBLEM TO BE SOLVED: To reduce the number of millicode instructions and the number of machine cycles by generating a necessary value through the use of information in a general-purpose register, a condition code and a millicode flag. SOLUTION: A cache memory unit 12 logically contains a writable inner code array 13 where a continuous address can be designated and millimode routines which are frequently called are stored in the inner code array 13. When a system enters a millimode millicode routine, one or plural conversion fetch (TPFET) millicode instruction supports a conversion/test (TRT) instruction. The TRFET instruction follows an ESA/390 architecture and generates the necessary value by using information in a general-purpose register, a condition code and a millicode flag. Thus, the general-purpose registers 1 of the processor and the condition code are updated.

    METHOD FOR CONTROLLING MILLI-MODE BY BRANCH HISTORY TABLE DISABLE
    4.
    发明专利
    METHOD FOR CONTROLLING MILLI-MODE BY BRANCH HISTORY TABLE DISABLE 失效

    公开(公告)号：JP2000112753A

    公开(公告)日：2000-04-21

    申请号：JP11053699

    申请日：1999-04-19

    Applicant: IBM

    Inventor： MARK A CHECK ,  JOHN S RIPPUTAI ,  TIMOTHY J SLEEGEL ,  CHARLES F WEBB ,  MARK S FARRELL

    IPC: G06F9/22 ,  G06F9/26 ,  G06F9/318 ,  G06F9/38

    Abstract: PROBLEM TO BE SOLVED: To obtain a method for operating a computer that has a milli-mode function by giving control, that enables a BHT operation to continue, to a milli-code except in the case of a specific situation where the control of an instruction fetch operation is needed. SOLUTION: A searching means 6 supplies a start address that is used when a branch history table(BHT) 5 accesses a BHT array 8 to the table (BHT) 5 which supplies information that gives an instruction to an instruction fetching means 2. Target information is latched in a register 10, and instruction address information is compared with a search address by a comparator 9. Results of the instruction address comparator 9 and a global disable latch 13 are used to decide if hit takes place and which set is desirable in hit detection logic 12. The selection of the set is used to control a multiplexer 11 and to make the instruction fetching means 2 gate correct branch target information.

    MILLIMODE SYSTEM HAVING BRANCH HISTORY TABLE DISABLING FUNCTION
    5.
    发明专利
    MILLIMODE SYSTEM HAVING BRANCH HISTORY TABLE DISABLING FUNCTION 失效

    公开(公告)号：JP2000099325A

    公开(公告)日：2000-04-07

    申请号：JP11055499

    申请日：1999-04-19

    Applicant: IBM

    Inventor： MARK A CHECK ,  JOHN S RIPPUTAI ,  TIMOTHY J SLEEGEL ,  CHARLES F WEBB ,  MARK S FARRELL

    IPC: G06F9/22 ,  G06F9/26 ,  G06F9/38

    Abstract: PROBLEM TO BE SOLVED: To provide a computer which has a millimode function for a system that has a central processor and also has operations of both normal mode and millimode. SOLUTION: This computer system having a millimode function gives the control to a millicode to continue a BHT(branch history table) operation excluding a case where a special situation occurs to need the control of an instruction fetch operation. A BHT 5 can be turned off to a certain section for execution of a code and cannot be disabled to all sections. A single free-running BHT functions to both normal mode and millimode used for a central processor that can be executed in a millimode by the BHT which indicates an instruction fetch containing both global BHT and millicode disabling functions.

    SYSTEM SERIALIZATION METHOD BY EARLY RELEASE OF INDIVIDUAL PROCESSOR
    6.
    发明专利
    SYSTEM SERIALIZATION METHOD BY EARLY RELEASE OF INDIVIDUAL PROCESSOR 失效

    公开(公告)号：JP2000029857A

    公开(公告)日：2000-01-28

    申请号：JP11471499

    申请日：1999-04-22

    Applicant: IBM

    Inventor： CHARLES F WEBB ,  DEAN G BAYER ,  MARK S FARRELL ,  BARRY W CRAN ,  PARK KIN MAKU ,  JENNIFER A NAVARO

    IPC: G06F15/177 ,  G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F9/52

    Abstract: PROBLEM TO BE SOLVED: To provide a system serialization method by the early release of individual processors by generating a system standstill request and the request of the updating of a global resource by the processor, responding to the request and buffering the request in the processor during the processing. SOLUTION: Plural CPUs 210 and 211 in a system respectively execute an instruction from a simple instruction set and the instruction from a complicated instruction set in the execution controller 243 of hardware control. The respective CPUs 210 and 211 generate the system standstill request and the request of the updating of the global resource and respond to the request. Then, during the processing, the system standstill request and the request of the updating of the global resource are buffered in one or more of the CPUs 210 and 211. A system operation controller provided with a system serialization controller 220 or the like instructs the updating the global resource.

    MULTIPROCESSOR SYSTEM
    7.
    发明专利
    MULTIPROCESSOR SYSTEM 失效

    公开(公告)号：JP2000010942A

    公开(公告)日：2000-01-14

    申请号：JP11473199

    申请日：1999-04-22

    Applicant: IBM

    Inventor： CHARLES F WEBB ,  DEAN G BAYER ,  MARK S FARRELL ,  BARRY W CRAN ,  PARK KIN MAKU ,  JENNIFER A NAVARO ,  TIMOTHY J SLEEGEL

    IPC: G06F9/52 ,  G06F9/318 ,  G06F15/16

    Abstract: PROBLEM TO BE SOLVED: To obtain a system which performs system serialization by early releasing of a processor by buffering a system standstill request and a request for updating on the processor. SOLUTION: Plural processors are included in this system and respective processors generates system standstill requests and requests to update global resources and responds to the requests. The system standstill request and the request for updating are buffered by one or plural processors. Then a system operation controller including a storage device controller SC 212 and a system serializing a controller 220 indicates the updating of the global resources. The global resources include an address conversion table entry and a protection key.

    equipamento, método e produto de programa de computador para modificação de controle de instrumentação do tempo de execução a partir de um estado menos privilegiado
    8.
    发明专利
    equipamento, método e produto de programa de computador para modificação de controle de instrumentação do tempo de execução a partir de um estado menos privilegiado 未知

    公开(公告)号：BR112014022763A2

    公开(公告)日：2020-10-27

    申请号：BR112014022763

    申请日：2013-03-01

    Applicant: IBM

    Inventor： CHARLES W GAINEY JR ,  CHUNG-LUNG KEVIN SHUM ,  MARK S FARRELL ,  TIMOTHY J SLEGEL

    IPC: G06F11/34

    Abstract: equipamento, método e produto de programa de computador para modificação de controles de instrumentação do tempo de execução a partir de um estado menos privilegiado. concretizações da invenção referem-se à modificação de controles de instrumentação do tempo de execução (mric) a partir de um estado menos privilegiado. a instrução mric é buscada. a instrução mric inclui o endereço de um bloco de controle de instrumentação do tempo de execução (riccb). o riccb é buscado com base no endereço incluído na instrução mric. o riccb inclui valores para a modificação de um subconjunto de controles de instrumentação do tempo de execução do processador. o subconjunto de controles de instrumentação do tempo de execução inclui um endereço atual de buffer (memória intermediária) de programa de instrumentação do tempo de execução (rca) de um local de buffer de programa de instrumentação do tempo de execução (rib). o rib contém informação da instrumentação do tempo de execução dos eventos reconhecidos pelo processador durante a execução do programa. os valores do riccb são carregados para os controles de instrumentação do tempo de execução. informação do evento é fornecida ao rib com base nos valores que foram carregados para o controle de instrumentação do tempo de execução.

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