公开(公告)号：AT504942T

公开(公告)日：2011-04-15

申请号：AT05737717

申请日：2005-02-23

Applicant: IBM

Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK ,  HORAK DAVID ,  KOBURGER III CHARLES ,  MASTERS MARK ,  MITCHELL PETER ,  POLONSKY STANISLAV

IPC: H01L21/768 ,  H01L21/285 ,  H01L23/522

Abstract: Conductive paths in an integrated circuit are formed using multiple undifferentiated carbon nanotubes embedded in a conductive metal, which is preferably copper. Preferably, conductive paths include vias running between conductive layers. Preferably, composite vias are formed by forming a metal catalyst pad on a conductor at the via site, depositing and etching a dielectric layer to form a cavity, growing substantially parallel carbon nanotubes on the catalyst in the cavity, and filling the remaining voids in the cavity with copper. The next conductive layer is then formed over the via hole.

公开(公告)号：AU2002357881A1

公开(公告)日：2004-07-29

申请号：AU2002357881

申请日：2002-12-17

Applicant: IBM

Inventor： MCCULLEN JUDITH H ,  PRUE SARAH ,  SITKO MICHAEL H ,  BOUCHER MATT ,  COHN JOHN M ,  DAUPHIN RICHARD ,  MASTERS MARK

IPC: G06F9/45 ,  G06F17/50 ,  G06K9/00 ,  G06T7/00

Abstract: The invention provides a method, system (12), and program product for diagnosing an integrated circuit. In particular, the invention captures one or more images for each relevant circuit layer of the integrated circuit (S2). Based on the image(s), a component netlist is generated (S3, S305, S315). Further, a logic netlist is generated (S4) by applying hierarchical composition rules to the component netlist. The component netlist and/or logic netlist can be compared to a reference netlist to diagnose the integrated circuit. The invention can further generate a schematic (50) based on the component netlist or logic netlist in which components are arranged according to port, power, and/or component pin connection information determined from the netlist. Further, the schematic can be displayed in a manner that wiring connections are selectively displayed to assist a user in intelligently arranging the circuit components.