公开(公告)号：EP1910954A4

公开(公告)日：2012-04-11

申请号：EP06800366

申请日：2006-07-26

Applicant: IBM

Inventor： CHIDAMBARRAO DURESETI ,  JORDAN DONALD L ,  MCCULLEN JUDITH H ,  ONSONGO DAVID M ,  WAGNER TINA ,  WILLIAMS RICHARD Q

IPC: G06F7/48 ,  G06F17/50

CPC classification number: G06F17/5068 ,  G06F17/5036 ,  H01L29/7843

公开(公告)号：WO2007016183A3

公开(公告)日：2008-12-18

申请号：PCT/US2006029069

申请日：2006-07-26

Applicant: IBM ,  CHIDAMBARRAO DURESETI ,  JORDAN DONALD L ,  MCCULLEN JUDITH H ,  ONSONGO DAVID M ,  WAGNER TINA ,  WILLIAMS RICHARD Q

Inventor： CHIDAMBARRAO DURESETI ,  JORDAN DONALD L ,  MCCULLEN JUDITH H ,  ONSONGO DAVID M ,  WAGNER TINA ,  WILLIAMS RICHARD Q

IPC: G06F7/48

CPC classification number: G06F17/5068 ,  G06F17/5036 ,  H01L29/7843

Abstract: System and method for compact model algorithms (310-350) to accurately account for effects of layout-induced changes in nitride liner (260) stress in semiconductor devices (200). The layout- sensitive compact model algorithms (310-350) account for the impact of large layout variation on circuits by implementing algorithms for obtaining the correct stress response approximations and layout extraction algorithms for obtaining the correct geometric parameters that drive the stress response. In particular, these algorithms include specific information from search "buckets" that are directionally-oriented and include directionally-specific distance measurements for analyzing in detail the specific shape neighborhood of the semiconductor device. The algorithms are additionally adapted to enable the modeling and stress impact determination of a device having single stress liner film and dual-stress liners (260) (two different liner films that abut at an interface).

Abstract translation: 用于紧凑模型算法（310-350）的系统和方法来准确地说明半导体器件（200）中氮化物衬垫（260）应力的布局引起的变化的影响。 布局敏感的紧凑模型算法（310-350）通过实现用于获得正确的应力响应近似和布局提取算法的算法来解决大布局变化对电路的影响，以获得驱动应力响应的正确几何参数。 特别地，这些算法包括来自定向定向的搜索“桶”的特定信息，并且包括用于详细分析半导体器件的特定形状邻域的定向特定的距离测量。 这些算法还适用于能够确定具有单个应力衬垫膜和双应力衬垫（260）（在界面处邻接的两个不同衬垫膜）的器件的建模和应力冲击测定。

公开(公告)号：AU2002357881A1

公开(公告)日：2004-07-29

申请号：AU2002357881

申请日：2002-12-17

Applicant: IBM

Inventor： MCCULLEN JUDITH H ,  PRUE SARAH ,  SITKO MICHAEL H ,  BOUCHER MATT ,  COHN JOHN M ,  DAUPHIN RICHARD ,  MASTERS MARK

IPC: G06F9/45 ,  G06F17/50 ,  G06K9/00 ,  G06T7/00

Abstract: The invention provides a method, system (12), and program product for diagnosing an integrated circuit. In particular, the invention captures one or more images for each relevant circuit layer of the integrated circuit (S2). Based on the image(s), a component netlist is generated (S3, S305, S315). Further, a logic netlist is generated (S4) by applying hierarchical composition rules to the component netlist. The component netlist and/or logic netlist can be compared to a reference netlist to diagnose the integrated circuit. The invention can further generate a schematic (50) based on the component netlist or logic netlist in which components are arranged according to port, power, and/or component pin connection information determined from the netlist. Further, the schematic can be displayed in a manner that wiring connections are selectively displayed to assist a user in intelligently arranging the circuit components.