1.
    发明专利
    未知

    公开(公告)号:AT504942T

    公开(公告)日:2011-04-15

    申请号:AT05737717

    申请日:2005-02-23

    Applicant: IBM

    Abstract: Conductive paths in an integrated circuit are formed using multiple undifferentiated carbon nanotubes embedded in a conductive metal, which is preferably copper. Preferably, conductive paths include vias running between conductive layers. Preferably, composite vias are formed by forming a metal catalyst pad on a conductor at the via site, depositing and etching a dielectric layer to form a cavity, growing substantially parallel carbon nanotubes on the catalyst in the cavity, and filling the remaining voids in the cavity with copper. The next conductive layer is then formed over the via hole.

    2.
    发明专利
    未知

    公开(公告)号:DE602005007592D1

    公开(公告)日:2008-07-31

    申请号:DE602005007592

    申请日:2005-03-22

    Applicant: IBM

    Abstract: A silicon-on-insulator (SOI) device and structure having locally strained regions in the silicon active layer formed by increasing the thickness of underlying regions of a buried insulating layer separating the silicon active layer from the substrate. The stress transferred from the underlying thickened regions of the insulating layer to the overlying strained regions increases carrier mobility in these confined regions of the active layer. Devices formed in and on the silicon active layer may benefit from the increased carrier mobility in the spaced-apart strained regions.

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