公开(公告)号：EP2357654A4

公开(公告)日：2012-08-29

申请号：EP09823395

申请日：2009-08-04

Applicant: IBM

Inventor： MIYATAKE HISATADA

IPC: G11C15/04 ,  G06F11/10

CPC classification number: G11C15/04 ,  G06F11/1064

公开(公告)号：EP1626412A4

公开(公告)日：2006-08-30

申请号：EP04727148

申请日：2004-04-13

Applicant: IBM

Inventor： SUNAGA TOSHIO ,  HOSOKAWA KOHJI ,  MIYATAKE HISATADA

IPC: G11C11/406

CPC classification number: G11C11/406

Abstract: It is possible to realize a DRAM of a simple circuit structure capable of effectively reducing the refresh current by setting the refresh cycle by a small step. A memory array is divided into 64 sub-arrays, each of which is further divided into eight blocks. A refresh cycle control circuit (RCCC) includes: a fuse circuit (FC0) for setting 1 or 1/2 division ratio; a divider (FD0) for dividing a pre-decode signal(ZLI0) with the division ratio which has been set; fuse circuits (FC1 to FC8) for setting 1 or 1/4 division ratio; and dividers (FD1 to FD8) for dividing pre-decode signals (ZLI1 to ZLI8) with the set division ratio. The refresh cycle control circuit (RCCC) can set the 64 or 128 ms refresh cycle for the 64 sub-arrays and the 64 or 256 ms refresh cycle for the 512 blocks.

Abstract translation: 可以通过以较小的步长设置刷新周期来实现能够有效地降低刷新电流的简单电路结构的DRAM。 存储器阵列被分成64个子阵列，每个阵列又被分成8个块。 刷新周期控制电路（RCCC）包括：用于设定1或1/2分频比的熔丝电路（FC0） 分频器（FD0），用于以已经设定的分频比对预解码信号（ZLI0）进行分频; 用于设置1或1/4分频比的熔丝电路（FC1至FC8）; 和分频器（FD1到FD8），用于以设定的分频比分割预解码信号（ZLI1到ZLI8）。 刷新周期控制电路（RCCC）可以为64个子阵列设置64或128 ms的刷新周期，并为512个块设置64或256 ms的刷新周期。

公开(公告)号：EP1463118A4

公开(公告)日：2008-07-02

申请号：EP02777998

申请日：2002-10-29

Applicant: IBM

Inventor： KIRAMURA KOHJI ,  SUNAGA TOSHIO ,  MIYATAKE HISATADA

IPC: G11C11/15 ,  G11C11/36 ,  H01L21/336 ,  H01L21/84 ,  H01L27/10 ,  H01L27/105 ,  H01L27/146 ,  H01L27/22

CPC classification number: H01L27/224 ,  H01L21/84

Abstract: An MRAM memory cell structure for preventing a parasitic transistor from generating. A diode is used as an MRAM memory cell switching element to form an n-type semiconductor layer (25) and a p-type semiconductor layer (29) that constitute a diode on the surface semiconductor layer of an SOI substrate. The n-type semiconductor layer (25) and the p-type semiconductor layer (29) are disposed in a lateral direction and separated by an isolation region (5) for electrically isolating from other elements or the substrate.

公开(公告)号：JP2003016774A

公开(公告)日：2003-01-17

申请号：JP2001194227

申请日：2001-06-27

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： MIYATAKE HISATADA ,  NODA HIROYOSHI ,  UMEZAKI HIROSHI ,  ASANO HIDEO ,  SUNANAGA TOSHIO ,  KITAMURA TSUNEJI

IPC: G11C11/14 ,  G11C11/15 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08

Abstract: PROBLEM TO BE SOLVED: To solve such a problem that because a current is required to make to flow for each bit line when data are written simultaneously in a plurality of data bits belonging to the same column address, a current required for write-in is enlarged.
SOLUTION: This device comprises a plurality of pairs of bit line comprising a first bit line and a second bit line, a plurality of storage cells storing information in accordance with the direction of a current flowing in the pair of bit line, at least one current driving source connected to at least one of pairs of bit line and making to flow a current in the first bit line and the second bit line of which the directions of current are reverse each other, at least one switch circuit connecting pairs of bit line and pairs of bit line, and a control circuit controlling a connection state of the switch circuit in accordance with information stored in the storage cell.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：为了解决由于在属于同一列地址的多个数据位中同时写入数据时需要为每个位线流动电流的问题，写入所需的电流为 放大 解决方案：该装置包括多对位线，包括第一位线和第二位线，多个存储单元根据在一对位线中流动的电流的方向存储信息，至少一个电流 驱动源连接到位线对中的至少一个并使得流过第一位线中的电流，并且使电流方向彼此相反的第二位线，至少一个连接成对的位线和 一对位线，以及根据存储在存储单元中的信息来控制开关电路的连接状态的控制电路。

公开(公告)号：JP2002359355A

公开(公告)日：2002-12-13

申请号：JP2001159353

申请日：2001-05-28

Applicant: IBM

Inventor： KITAMURA TSUNEJI ,  SUNANAGA TOSHIO ,  MIYATAKE HISATADA

IPC: G11C11/14 ,  G11C11/15 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08

Abstract: PROBLEM TO BE SOLVED: To provide a nonvolatile magnetic memory cell having a multilayer structure and a storage circuit block using the same. SOLUTION: A nonvolatile magnetic memory cell 40 is constituted to include a second bit line 38b, a second storage device 10b which is connected to the second bit line 38b and includes a ferroelectric layer of which magnetization direction is changed by a direction of a magnetic field generated by an electric current that flows in the second bit line 38b, a second switching device 30b of which one end is connected to a third wiring structure 24, and a second wiring structure 22b which sandwiches the second storage device 10b with the second bit line 38b and allows the second storage device 10b and the other end of the second switching device 30b to connect to each other.

公开(公告)号：JPH06275066A

公开(公告)日：1994-09-30

申请号：JP6388893

申请日：1993-03-23

Applicant: IBM

Inventor： MIYATAKE HISATADA

IPC: G11C11/401 ,  G11C7/10 ,  G11C11/407

Abstract: PURPOSE: To realize memory access in the page mode of a single clock memory. CONSTITUTION: A control signal PAGE which is set to one level to indicate the normal mode and is set to the other to indicate the page mode is given to a single clock memory 10 from the outside. In a mode state discrimination circuit 14, the combination of levels of the control signal in two continuous address input cycles is decoded to discriminate four mode states of the normal mode, the page-in mode, the page mode, and the page-out mode. A memory control circuit part 18 of a memory array 16 is controlled based on the discrimination result.

公开(公告)号：CA2462940A1

公开(公告)日：2003-05-08

申请号：CA2462940

申请日：2002-10-29

Applicant: IBM

Inventor： KIRAMURA KOHJI ,  SUNAGA TOSHIO ,  MIYATAKE HISATADA

IPC: G11C11/15 ,  G11C11/36 ,  H01L21/336 ,  H01L21/84 ,  H01L27/10 ,  H01L27/105 ,  H01L27/146 ,  H01L27/22

Abstract: An MRAM memory cell structure for preventing a parasitic transistor from generating. A diode is used as an MRAM memory cell switching element to form an n-type semiconductor layer (25) and a p-type semiconductor layer (29) tha t constitute a diode on the surface semiconductor layer of an SOI substrate. T he n-type semiconductor layer (25) and the p-type semiconductor layer (29) are disposed in a lateral direction and separated by an isolation region (5) for electrically isolating from other elements or the substrate.

公开(公告)号：CA2462940C

公开(公告)日：2009-11-17

申请号：CA2462940

申请日：2002-10-29

Applicant: IBM

Inventor： KIRAMURA KOHJI ,  MIYATAKE HISATADA ,  SUNAGA TOSHIO

IPC: H01L27/10 ,  G11C11/15 ,  G11C11/36 ,  H01L21/336 ,  H01L21/84 ,  H01L27/105 ,  H01L27/146 ,  H01L27/22

Abstract: Provided is an MRAM memory cell structure capable of preventing generation o f parasitic transistors. Diodes are adopted as switching elements of an MRAM memory cell. An n-type semiconductor layer and a p-type semiconductor layer, which collectively constitute a diod e, are formed on a surface semiconductor layer of an SOI substrate. The n-type semiconductor layer and the p-type semiconductor layer are disposed in a lateral direction and isolated by an isolation region, whereby the diode is isolated electrically from other elements and from the substrat e.

公开(公告)号：JP2007066490A

公开(公告)日：2007-03-15

申请号：JP2005254878

申请日：2005-09-02

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： MIYATAKE HISATADA

IPC: G11C11/407 ,  G11C11/403

CPC classification number: G11C11/406 ,  G11C11/40603 ,  G11C11/40615

Abstract: PROBLEM TO BE SOLVED: To provide a pseudo SRAM in which request of external access and request of refresh can be mediated.
SOLUTION: The semiconductor memory device is provided with an access standby circuit 20 generating an access standby signal/ECP in accordance with an external access request signal/CE or the like, an access start circuit 21 generating an access start signal/AE in accordance with an L level of the access standby signal/ECP and an H level of a busy signal/BUSY, a refresh standby circuit 22 generating a refresh standby signal/REFP in accordance with a refresh request signal/REFT, and a refresh start circuit 23 generating a refresh start signal/REFE in accordance with an H level of the access standby signal/ECP, an L level of the refresh standby signal/REFP, and an H level of the busy signal/BUSY. An array control circuit 12 performs access operation in accordance with an access start signal/AE, and performs refresh operation in accordance with the refresh start signal/REFE.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供可以介导外部访问请求和刷新请求的伪SRAM。 解决方案：半导体存储器件设置有根据外部访问请求信号/ CE等生成访问备用信号/ ECP的访问备用电路20，生成访问开始信号/ AE的访问启动电路21 根据访问待机信号/ ECP的L电平和忙信号/ BUSY的H电平，根据刷新请求信号/ REFT产生刷新待机信号/ REFP的刷新待机电路22和刷新开始 电路23根据访问待机信号/ ECP的H电平，刷新待机信号/ REFP的L电平和忙信号/ BUSY的H电平产生刷新开始信号/ REFE。 阵列控制电路12根据访问开始信号/ AE执行访问操作，并且根据刷新开始信号/ REFE执行刷新操作。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2003017662A

公开(公告)日：2003-01-17

申请号：JP2001193866

申请日：2001-06-27

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： MIYATAKE HISATADA ,  SUNANAGA TOSHIO ,  KITAMURA TSUNEJI

IPC: G11C11/14 ,  G11C11/15 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L43/08

Abstract: PROBLEM TO BE SOLVED: To provide a memory cell capable of reducing a writing current, to provide a storage circuit block, and to provide a method for writing data.
SOLUTION: Related to a memory cell 12, a second bit line 15 is provided at the position where a storage element 28 is clamped with a bit line 14. The second bit line 15 is at least parallel to the first bit line 14 near the storage element 28, while not contacting to the storage element 28.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：提供能够减小写入电流的存储单元，提供存储电路块，以及提供写入数据的方法。 解决方案：与存储器单元12相关，第二位线15设置在存储元件28被位线14夹持的位置处。第二位线15至少与存储器附近的第一位线14平行 元件28，而不与存储元件28接触。