公开(公告)号：US3509366A

公开(公告)日：1970-04-28

申请号：US3509366D

申请日：1967-02-23

Applicant: IBM

Inventor： HOWE LELAND D JR ,  MOYER JAMES T

IPC: H03K3/037 ,  H03K19/22 ,  H03K19/40

CPC classification number: H03K3/037

公开(公告)号：US3303476A

公开(公告)日：1967-02-07

申请号：US35738364

申请日：1964-04-06

Applicant: IBM

Inventor： MOYER JAMES T ,  RAUSCH FRANCIS R

IPC: G06F3/00 ,  G06F3/12 ,  G06F9/22 ,  G06F9/26 ,  G06F9/32 ,  G06F12/14 ,  G06F13/22 ,  G06F13/26 ,  G06F13/38

CPC classification number: G06F9/30094 ,  G06F3/00 ,  G06F3/12 ,  G06F3/1293 ,  G06F9/226 ,  G06F9/261 ,  G06F9/30058 ,  G06F12/1466 ,  G06F13/22 ,  G06F13/26 ,  G06F13/38

公开(公告)号：FR2399064A1

公开(公告)日：1979-02-23

申请号：FR7819407

申请日：1978-06-20

Applicant: IBM

Inventor： MOYER JAMES T

IPC: G06F3/06 ,  G06F5/06 ,  G06F12/08 ,  G06F13/12 ,  G06F13/00 ,  G11C7/00 ,  G11C9/00

Abstract: Channel data buffer apparatus for buffering data being transferred between an input/output channel unit and a main storage unit in a digital data processing system. In the disclosed embodiment, data is generally transferred between the channel unit and the data buffer (a "channel/buffer" transfer) in two-byte segments and between the main storage unit and the data buffer (a "storage/buffer" transfer) in eight-byte segments. The data buffer is comprised of eight column-forming byte-wide multirow storage arrays each having its own address mechanism for accessing any desired row therein. Corresponding rows in the different storage arrays provide the corresponding eight-byte rows for the data buffer as a whole. For storage/buffer transfers, data buffer address circuitry is provided for enabling a group of eight contiguous bytes to be read out of or written into the data buffer on a single access even though some of the bytes may be located on one row of the data buffer and other of the bytes on the next row of the data buffer. For channel/buffer transfers, data buffer address circuitry is provided for enabling a group of two contiguous bytes to be read out of or written into the data buffer on a single access even though one of the bytes may be located on one row of the data buffer and the other of the bytes on the next row of the data buffer. For storage/buffer transfers, an eight-byte wrap-around data shifter is located between the data buffer and the main storage unit for enabling any necessary alignment or realignment of the data being transferred. These features enable data to be loaded into the data buffer in a packed manner and without regard to the storage word boundary alignments in the main storage unit. Among other things, this minimizes the hardware needed for buffering the data and improves the data chaining capability of the system.

公开(公告)号：CA1213065A

公开(公告)日：1986-10-21

申请号：CA454740

申请日：1984-05-18

Applicant: IBM

Inventor： JACKOWSKI STEFAN P ,  MOYER JAMES T

IPC: G06F13/00 ,  G01R31/28 ,  G06F11/00 ,  G06F11/16 ,  G06F13/36

Abstract: The invention determines the existence of abnormal circuit conditions in lines of a group of interface lines without using redundant duplex lines. The interface lines are subdivided into a first group, used when the present invention is being used to locate abnormal circuit conditions, and a second group, which is not used when the present invention is being used to locate abnormal circuit conditions. Each first group line is connected to a corresponding input terminal of a first exclusive or gate and a second exclusive or gate at an input and output, respectively. The first and second or gates are input to a matching circuit, an output signal therefrom indicating an abnormal circuit condition in the first line group. As a result, since the first group lines are used when the present invention is being used to locate abnormal circuit conditions, each first group line is tested individually for an abnormal circuit condition. However, since lines of the second group are not used when the invention is locating abnormal circuit conditions, lines of the second group are tested, collectively for an abnormal circuit condition. One line of the first group is connected to an input of the second group. The output of the second group is connected to an additional input of the second exclusive or gate. An output signal from the matching circuit indicates the existence of an abnormal circuit condition in at least one line of either one or both of the first and second group of lines.

公开(公告)号：CA869131A

公开(公告)日：1971-04-20

申请号：CA869131D

Applicant: IBM

Inventor： HOWE LELAND D JR ,  MOYER JAMES T

公开(公告)号：CA776322A

公开(公告)日：1968-01-16

申请号：CA776322D

Applicant: IBM

Inventor： MOYER JAMES T ,  RAUSCH FRANCIS R

公开(公告)号：CA1315890C

公开(公告)日：1993-04-06

申请号：CA598603

申请日：1989-05-03

Applicant: IBM

Inventor： CHISHOLM DOUGLAS R ,  ISEMINGER ROBERT G ,  KELLEY RICHARD A ,  LEUNG WAN L ,  MOYER JAMES T ,  SNEDAKER MARK C

IPC: G06F13/36 ,  G06F13/28

Abstract: In a computer system, a plurality of input/output processors (IOP's) are connected via an asynchronous input/output bus, called an "SPD" bus, to one side of an input/output interface controller (IOIC). The other side of the IOIC is connected to a storage controller (SC) via a synchronous bus called an "adapter" bus. The SC is connected to a common system memory and possibly also to an instruction processing unit. The SPD bus, which comprises three sub-buses and a control bus, conducts signals between each IOP and the IOIC in an asynchronous "handshaking" manner. The adapter bus, which comprises two sub-buses and a control bus, conducts signals between the IOIC and the SC in a synchronous manner. The IOIC, interconnected between the SPD bus and adapter bus, functions as a buffer between the faster synchronous bus and the slower asychronous bus. The IOIC also comprises at least one shared DMA facility for executing DMA storage operations requested by the IOP's via the SPD bus. Each shared DMA facility includes a buffer for control information and data to be transmitted between the SC and one of the IOP's and a bus interface coupled to the buffer, to the adapter bus and to the SPD bus for independently transferring the control information and data between the buffer and the SC, on one hand, via the adapter bus, and between the buffer and the one IOP, on the other hand, via the SPD bus. In this manner, the SPD bus can be released for utilization by other IOP's connected thereto during a period of "storage latency" after a DMA storage operation has been initiated by one IOP.

公开(公告)号：CA1102006A

公开(公告)日：1981-05-26

申请号：CA301808

申请日：1978-04-24

Applicant: IBM

Inventor： MOYER JAMES T

IPC: G06F3/06 ,  G06F5/06 ,  G06F12/08 ,  G06F13/12 ,  G06F3/00 ,  G06F13/00

Abstract: CHANNEL DATA BUFFER APPARATUS FOR A DIGITAL DATA PROCESSING SYSTEM Channel data buffer apparatus for buffering data being transferred between an input/output channel unit and a main storage unit in a digital data processing system. In the disclosed embodiment, data is generally transferred between the channel unit and the data buffer (a "channel/buffer" transfer) in two-byte segments and between the main storage unit and the data buffer (a "storage/buffer" transfer) in eight-byte segments. The data buffer is comprised of eight columnforming byte-wide multirow storage arrays each having its own address mechanism for accessing any desired row therein. Corresponding rows in the different storage arrays provide the corresponding eight-byte rows for the data buffer as a whole. For storage/buffer transfers, data buffer address circuitry is provided for enabling a group of eight contiguous bytes to be read out of or written into the data buffer on a single access even though some of the bytes may be located on one row of the data buffer and other of the bytes on the next row of the data buffer. For channel/buffer transfers, data buffer address circuitry is provided for enabling a group of two contiguous bytes to be read out of or written into the data buffer on a single access even though one of the bytes may be located on one row of the data buffer and the other of the bytes on the next row of the data buffer. For storage/buffer transfers, an eight-byte wrap-around data shifter is located between the data buffer and the main storage unit for enabling any necessary alignment or realignment of the data being transferred. These features enable data to be loaded into the data buffer in a packed manner and without regard to the storage word boundary alignments in the main storage unit. Among other things, this minimizes the hardware needed for buffering the data and improves the data chaining capability of the system.