公开(公告)号：AU2010236920A1

公开(公告)日：2011-08-25

申请号：AU2010236920

申请日：2010-03-18

Applicant: IBM

Inventor： CAMPI JOHN B ,  CHANG SHUNHUA T ,  CHATTY KIRAN V ,  GAUTHIER ROBERT J ,  JUNJUN LI ,  MUJAHID MUHAMAD

IPC: H01L21/336 ,  H01L23/60

Abstract: A robust ESD protection circuit, method and design structure for tolerant and failsafe designs are disclosed. A circuit (200) includes a middle junction control circuit (250) that turns off a top NFET (225) of a stacked NFET electrostatic discharge (ESD) protection circuit (pad 215, ground 220, top NFET 225, bottom NFET 230, top resistor 235, and bottom resistor 240) during an ESD event.