公开(公告)号：GB2605234A

公开(公告)日：2022-09-28

申请号：GB202116911

申请日：2021-11-24

Applicant: IBM

Inventor： HONGQING ZHANG ,  JAY A BUNT ,  SHIDONG LI ,  ZHIGANG SONG ,  GUODA LIAN ,  JUNJUN LI

IPC: H05K1/02 ,  G06F21/86

Abstract: Tamper-respondent assembly including circuit board 610, electronic component 602 and enclosure assembly 620 coupled to circuit board 610 to enclose electronic component 602 within a secure volume 601. Enclosure assembly 620 includes an enclosure with a sealed inner compartment 623 containing a structural material 701. Structural material 701 inhibits deflection of the enclosure due to a pressure differential between the sealed inner compartment 623 and around the enclosure 620. Pressure sensor 640 sense pressure within sealed inner compartment 623 to facilitate identification of a pressure change indicative of a tamper event. Optionally, structural material 701 may comprise a foam metal with interconnected pores. Enclosure 620 may comprise a metal enclosure with inner and outer walls. Foam metal within the sealed inner compartment 623 may be diffusion bonded to these walls. Sealed inner compartment 623 may comprise two sealed inner chambers of differing pressures, both containing structural material 701. A monitor circuit may be positioned within secure volume 601 to monitor the pressure of sealed inner compartment 623 via pressure sensor 640.

公开(公告)号：AU2010236920A1

公开(公告)日：2011-08-25

申请号：AU2010236920

申请日：2010-03-18

Applicant: IBM

Inventor： CAMPI JOHN B ,  CHANG SHUNHUA T ,  CHATTY KIRAN V ,  GAUTHIER ROBERT J ,  JUNJUN LI ,  MUJAHID MUHAMAD

IPC: H01L21/336 ,  H01L23/60

Abstract: A robust ESD protection circuit, method and design structure for tolerant and failsafe designs are disclosed. A circuit (200) includes a middle junction control circuit (250) that turns off a top NFET (225) of a stacked NFET electrostatic discharge (ESD) protection circuit (pad 215, ground 220, top NFET 225, bottom NFET 230, top resistor 235, and bottom resistor 240) during an ESD event.