公开(公告)号：EP2404316A4

公开(公告)日：2016-04-06

申请号：EP10770142

申请日：2010-04-22

Applicant: IBM

Inventor： GREENE BRIAN J ,  CHUDZIK MICHAEL P ,  HAN SHU-JEN ,  HENSON WILLIAM K ,  LIANG YUE ,  MACIEJEWSKI EDWARD P ,  NA MYUNG-HEE ,  NOWAK EDWARD J ,  YU XIAOJUN

IPC: H01L21/8234 ,  H01L21/28 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L21/823462 ,  H01L21/28229 ,  H01L21/84 ,  H01L27/1203

公开(公告)号：SG174853A1

公开(公告)日：2011-11-28

申请号：SG2011057296

申请日：2010-04-22

Applicant: IBM

Inventor： GREENE BRIAN J ,  CHUDZIK MICHAEL P ,  HAN SHU-JEN ,  HENSON WILLIAM K ,  LIANG YUE ,  MACIEJEWSKI EDWARD P ,  NA MYUNG-HEE ,  NOWAK EDWARD J ,  YU XIAOJUN

Abstract: Multiple types of gate stacks are formed on a doped semiconductor well. A high dielectric constant (high-k) gate dielectric is formed on the doped semiconductor well. A metal gate layer is formed in one device area, while the high-k gate dielectric is exposed in other device areas. Threshold voltage adjustment oxide layers having different thicknesses are formed in the other device areas. A conductive gate material layer is then formed over the threshold voltage adjustment oxide layers. One type of field effect transistors includes a gate dielectric including a high-k gate dielectric portion. Other types of field effect transistors include a gate dielectric including a high-k gate dielectric portion and a first threshold voltage adjustment oxide portions having different thicknesses. Field effect transistors having different threshold voltages are provided by employing different gate dielectric stacks and doped semiconductor wells having the same dopant concentration.

公开(公告)号：BRPI1007604A2

公开(公告)日：2016-02-16

申请号：BRPI1007604

申请日：2010-04-22

Applicant: IBM

Inventor： GREENE BRIAN J ,  NOWAK EDWARD J ,  MACIEJEWSKI EDWARD P ,  CHUDZIK MICHAEL P ,  NA MYUNG-HEE ,  HAN SHU-JEN ,  HENSON WILLIAM K ,  YU XIAOJUN ,  LIANG YUE

IPC: H01L21/283 ,  H01L29/49

公开(公告)号：CA2750215A1

公开(公告)日：2010-11-04

申请号：CA2750215

申请日：2010-04-22

Applicant: IBM

Inventor： GREENE BRIAN J ,  CHUDZIK MICHAEL P ,  HAN SHU-JEN ,  HENSON WILLIAM K ,  LIANG YUE ,  MACIEJEWSKI EDWARD P ,  NA MYUNG-HEE ,  NOWAK EDWARD J ,  YU XIAOJUN

IPC: H01L21/71 ,  H01L21/77 ,  H01L27/085 ,  H01L27/098

Abstract: Multiple types of gate stacks (100,..., 600) are formed on a doped semiconductor well. A high dielectric constant (high-k) gate dielectric (30L) is formed on the doped semiconductor well (22, 24). A metal gate layer (42L) is formed in one device area, while the high-k gate dielectric is exposed in other device areas (200, 400, 500, 600). Threshold voltage adjustment oxide layers having different thicknesses are formed in the other device areas. A conductive gate material layer (72L) is then formed over the threshold voltage adjustment oxide layers. One type of field effect transistors includes a gate dielectric including a high-k gate dielectric portion. Other types of field effect transistors include a gate dielectric including a high-k gate dielectric portion and a first threshold voltage adjustment oxide portions having different thicknesses. Field effect transistors having different threshold voltages are provided by employing different gate dielectric stacks and doped semiconductor wells having the same dopant concentration.