公开(公告)号：EP2145349A4

公开(公告)日：2012-03-28

申请号：EP08754077

申请日：2008-04-08

Applicant: IBM

Inventor： CHUDZIK MICHAEL P ,  DORIS BRUCE B ,  HENSON WILLIAM K ,  YAN HONGWEN ,  ZHANG YING

IPC: H01L21/20 ,  H01L21/28 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/04

CPC classification number: H01L29/045 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28097 ,  H01L21/31138 ,  H01L21/32137 ,  H01L21/32139 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/84

公开(公告)号：EP2419925A4

公开(公告)日：2016-03-30

申请号：EP10765059

申请日：2010-04-14

Applicant: IBM

Inventor： CHUDZIK MICHAEL P ,  HENSON WILLIAM K ,  JHA RASHMI ,  LIANG YUE ,  RAMACHANDRAN RAVIKUMAR ,  WISE RICHARD S

IPC: H01L21/8238 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L29/517 ,  H01L21/28185 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/49 ,  H01L29/7833

Abstract: The present invention, in one embodiment, provides a method of forming a semiconductor device that includes providing a substrate including a first conductivity type region and a second conductivity type region; forming a gate stack including a gate dielectric atop the first conductivity type region and the second conductivity type region of the substrate and a first metal gate conductor overlying the high-k gate dielectric; removing a portion of the first metal gate conductor that is present in the first conductivity type region to expose the gate dielectric present in the first conductivity type region; applying a nitrogen based plasma to the substrate, wherein the nitrogen based plasma nitrides the gate dielectric that is present in the first conductivity type region and nitrides the first metal gate conductor that is present in the second conductivity type region; and forming a second metal gate conductor overlying at least the gate dielectric that is present in the first conductivity type region.

公开(公告)号：EP2404316A4

公开(公告)日：2016-04-06

申请号：EP10770142

申请日：2010-04-22

Applicant: IBM

Inventor： GREENE BRIAN J ,  CHUDZIK MICHAEL P ,  HAN SHU-JEN ,  HENSON WILLIAM K ,  LIANG YUE ,  MACIEJEWSKI EDWARD P ,  NA MYUNG-HEE ,  NOWAK EDWARD J ,  YU XIAOJUN

IPC: H01L21/8234 ,  H01L21/28 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L21/823462 ,  H01L21/28229 ,  H01L21/84 ,  H01L27/1203

公开(公告)号：EP2024995A4

公开(公告)日：2013-07-03

申请号：EP07797764

申请日：2007-05-25

Applicant: IBM

Inventor： CHIDAMBARRAO DURESETI ,  HENSON WILLIAM K ,  NG HUNG Y ,  RIM KERN ,  WANN CLEMENT H

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/764

CPC classification number: H01L21/764 ,  H01L21/76283

公开(公告)号：JP2010251742A

公开(公告)日：2010-11-04

申请号：JP2010075677

申请日：2010-03-29

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： MO RENEE T ,  CHUDZIK MICHAEL P ,  VIJAY NARAYANAN ,  HENSON WILLIAM K ,  KHARE MUKESH VIJAY ,  BU HUIMING

IPC: H01L21/8238 ,  H01L21/28 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L21/823807 ,  H01L21/28097 ,  H01L21/28194 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/1054 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66651 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a gate structure for improvement in device performance in a metal oxide film semiconductor field-effect transistor.
SOLUTION: A method of forming a semiconductor device is provided that includes forming a Ge-containing layer atop p-type device regions of the substrate. Thereafter, a first dielectric layer is formed in a second portion of a substrate, and a second dielectric layer is formed overlying the first dielectric layer in the second portion of the substrate and overlying a first portion of the substrate. Gate structures may then be formed atop the p-type device regions and n-type device regions of the substrate, and the gate structures to the n-type device regions include a rare-earth metal.
COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于改善金属氧化物半导体场效应晶体管的器件性能的栅极结构。 解决方案：提供一种形成半导体器件的方法，其包括在基板的p型器件区域的顶部形成Ge含有层。 此后，在衬底的第二部分中形成第一电介质层，并且在衬底的第二部分中覆盖第一介电层并覆盖衬底的第一部分上形成第二电介质层。 然后可以在衬底的p型器件区域和n型器件区域的顶部形成栅极结构，并且到n型器件区域的栅极结构包括稀土金属。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：WO2007140288A3

公开(公告)日：2008-04-24

申请号：PCT/US2007069720

申请日：2007-05-25

Applicant: IBM ,  CHIDAMBARRAO DURESETI ,  HENSON WILLIAM K ,  NG HUNG Y ,  RIM KERN ,  WANN CLEMENT H

Inventor： CHIDAMBARRAO DURESETI ,  HENSON WILLIAM K ,  NG HUNG Y ,  RIM KERN ,  WANN CLEMENT H

IPC: H01L21/76

CPC classification number: H01L21/764 ,  H01L21/76283

Abstract: The present invention relates to semiconductor-on-insulator (SOI) substrates having device regions (2, 4, 6), each comprises a base semiconductor substrate layer (12) and a semiconductor device layer (16) and a buried insulator layer (14) between. The semiconductor device layer (16) supported by vertical insulating pillars (22), each having a ledge extending between the base semiconductor substrate layer (12) and the semiconductor device layer (16). The SOI substrates of the present invention can be readily formed from a precursor substrate structure with a "floating" semiconductor device layer that is spaced apart from the base semiconductor substrate layer by an air gap (15) and is supported by the vertical insulating pillars (22). The air gap (15) is preferably formed by selective removal of a sacrificial layer (13) located between the base semiconductor substrate layer (12) and the semiconductor device layer (16).

Abstract translation: 本发明涉及具有器件区域（2,4,6）的绝缘体上绝缘体（SOI）衬底，每个衬底半导体衬底层（12）和半导体器件层（16）和掩埋绝缘体层（14） ）之间。 由垂直绝缘柱（22）支撑的半导体器件层（16）各自具有在基底半导体衬底层（12）和半导体器件层（16）之间延伸的凸缘。 本发明的SOI衬底可以容易地由具有“浮动”半导体器件层的前体衬底结构形成，半导体器件层通过气隙（15）与基底半导体衬底层间隔开并由垂直绝缘柱（ 22）。 气隙（15）优选通过选择性地去除位于基底半导体衬底层（12）和半导体器件层（16）之间的牺牲层（13）来形成。

公开(公告)号：DE112011103483T8

公开(公告)日：2013-10-02

申请号：DE112011103483

申请日：2011-07-27

Applicant: IBM

Inventor： WANG XINLIN ,  HENSON WILLIAM K ,  RIM KERN ,  LIANG YUE

IPC: H01L21/336 ,  H01L29/78

公开(公告)号：DE112012004134T5

公开(公告)日：2014-06-26

申请号：DE112012004134

申请日：2012-10-26

Applicant: IBM

Inventor： BRODSKY MARY JANE ,  CAI MING ,  GUO DECHAO ,  HENSON WILLIAM K ,  NARASIMHA SHREESH ,  LIANG YUE ,  SONG LIYANG ,  WANG YANFENG ,  YEH CHUN-CHEN

IPC: H01L29/786

Abstract: Eine Struktur beinhaltet ein Substrat; einen Transistor, der über dem Substrat angeordnet ist, wobei der Transistor eine Finne aufweist, die aus Silicium besteht, das mit Kohlenstoff implantiert ist; und eine Schicht eines Gate-Dielektrikums und eine Schicht eines Gate-Metalls, die über einem Abschnitt der Finne liegen, der einen Kanal des Transistors definiert. In der Struktur wird eine Kohlenstoffkonzentration innerhalb der Finne so gewählt, dass eine gewünschte Schwellenspannung des Transistors erreicht wird. Darüber hinaus werden Verfahren zum Fertigen eines FinFET-Transistors offenbart. Zudem wird ein planarer Transistor mit einer mit Kohlenstoff implantierten Wanne offenbart, wobei die Kohlenstoffkonzentration innerhalb der Wanne so gewählt wird, dass eine gewünschte Schwellenspannung des Transistors erreicht wird.

公开(公告)号：SG174853A1

公开(公告)日：2011-11-28

申请号：SG2011057296

申请日：2010-04-22

Applicant: IBM

Inventor： GREENE BRIAN J ,  CHUDZIK MICHAEL P ,  HAN SHU-JEN ,  HENSON WILLIAM K ,  LIANG YUE ,  MACIEJEWSKI EDWARD P ,  NA MYUNG-HEE ,  NOWAK EDWARD J ,  YU XIAOJUN

Abstract: Multiple types of gate stacks are formed on a doped semiconductor well. A high dielectric constant (high-k) gate dielectric is formed on the doped semiconductor well. A metal gate layer is formed in one device area, while the high-k gate dielectric is exposed in other device areas. Threshold voltage adjustment oxide layers having different thicknesses are formed in the other device areas. A conductive gate material layer is then formed over the threshold voltage adjustment oxide layers. One type of field effect transistors includes a gate dielectric including a high-k gate dielectric portion. Other types of field effect transistors include a gate dielectric including a high-k gate dielectric portion and a first threshold voltage adjustment oxide portions having different thicknesses. Field effect transistors having different threshold voltages are provided by employing different gate dielectric stacks and doped semiconductor wells having the same dopant concentration.

公开(公告)号：BRPI1007604A2

公开(公告)日：2016-02-16

申请号：BRPI1007604

申请日：2010-04-22

Applicant: IBM

Inventor： GREENE BRIAN J ,  NOWAK EDWARD J ,  MACIEJEWSKI EDWARD P ,  CHUDZIK MICHAEL P ,  NA MYUNG-HEE ,  HAN SHU-JEN ,  HENSON WILLIAM K ,  YU XIAOJUN ,  LIANG YUE

IPC: H01L21/283 ,  H01L29/49