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    Data processing system
    1.
    发明公开
    Data processing system 失效
    Datenverarbeitungssystem

    公开(公告)号：EP0801352A3

    公开(公告)日：1998-10-14

    申请号：EP97301904

    申请日：1997-03-20

    Applicant: IBM

    Inventor： GUTHRIE GUY LYNN ,  KELLEY RICHARD ALLEN ,  NEAL DANNY MARVIN ,  THURBER STEVE MARK

    IPC: G06F13/36 ,  G06F13/40

    CPC classification number: G06F13/36 ,  G06F13/4027

    Abstract: A data processing system 10 includes a processor 12, system memory 15 and a number of peripheral devices 401, 403, and one or more bridges 400 which may connect between the processor, memory and peripheral devices and other hosts or peripheral devices such as in a network. A bridge, such as a PCI host bridge, connects between a primary bus (e.g system bus) 14 and a secondary bus 16. The host bridge 400 provides a dual host bridge function which creates two secondary bus interfaces. This allows increased loading capability under one dual host bridge compared to a lesser number of slots allowed under one normal host bridge. Also included is additional control logic for providing arbitration control and for steering transactions to the appropriate bus interface. Additionally, peer to peer support across the two secondary bus interfaces is provided.

    Abstract translation: 数据处理系统10包括处理器12，系统存储器15和多个外围设备401,403，以及一个或多个桥接器400，其可以连接处理器，存储器和外围设备以及其他主机或外围设备，诸如 网络。 诸如PCI主桥之类的桥连接在主总线（例如系统总线）14和次总线16之间。主桥400提供双主桥功能，其创建两个次级总线接口。 这允许在一个双主桥下增加加载能力，而在一个正常主桥下允许的插槽数量较少。 还包括用于提供仲裁控制和将交易转向相应总线接口的附加控制逻辑。 此外，还提供了跨两个辅助总线接口的对等支持。

    Dma windowing in lpar environment using device arbitration level to allow multiple ioas per terminal bridge
    2.
    发明专利
    Dma windowing in lpar environment using device arbitration level to allow multiple ioas per terminal bridge 审中-公开
    使用设备仲裁级别的LPAR环境中的DMA窗口可以允许每个终端桥接多个IOAS

    公开(公告)号：JP2009193590A

    公开(公告)日：2009-08-27

    申请号：JP2009055764

    申请日：2009-03-09

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： ARNDT RICHARD LOUIS ,  NEAL DANNY MARVIN ,  THURBER STEVE MARK

    IPC: G06F12/14 ,  G06F9/46 ,  G06F13/36 ,  G06F15/177

    Abstract: PROBLEM TO BE SOLVED: To provide a method, system, and apparatus for preventing input/output (I/O) used by an operating system (OS) image, in a logically partitioned data processing system, from corrupting or fetching data allocated to another OS image within the system. SOLUTION: This logically partitioned data processing system includes a plurality of logical partitions, the plurality of operating systems (OS), a plurality of memory locations, a plurality of I/O adapters (IOA), and a hypervisor. Each of the operating system images is assigned to each of different logical partitions. Each of the memory locations and each of the input/output adapters are assigned to one of the logical partitions. The hypervisor prevents transmission of data between the input/output adapter in one of the logical partitions and the memory location assigned to the other logical partition during a direct memory access (DMA) operation by assigning each of the input/output adapters a range of I/O bus DMA addresses. COPYRIGHT: (C)2009,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种用于在逻辑分区的数据处理系统中防止操作系统（OS）图像使用的输入/输出（I / O）的方法，系统和装置，以破坏或获取数据 分配给系统中的另一个OS映像。 解决方案：该逻辑分区数据处理系统包括多个逻辑分区，多个操作系统（OS），多个存储器位置，多个I / O适配器（IOA）和管理程序。 每个操作系统映像被分配给每个不同的逻辑分区。 每个存储器位置和每个输入/输出适配器被分配给一个逻辑分区。 虚拟机管理程序防止在直接存储器访问（DMA）操作期间在逻辑分区之一的输入/输出适配器和分配给另一逻辑分区的存储器位置之间传输数据，通过将每个输入/输出适配器分配给I / O总线DMA地址。 版权所有（C）2009，JPO＆INPIT

    INFORMATION PROCESSING SYSTEM
    3.
    发明专利
    INFORMATION PROCESSING SYSTEM 失效

    公开(公告)号：JP2001022686A

    公开(公告)日：2001-01-26

    申请号：JP2000172663

    申请日：2000-06-08

    Applicant: IBM

    Inventor： KELLEY RICHARD A ,  NEAL DANNY MARVIN ,  THURBER STEVEN MARK ,  ADARUBAATOU GIRAAMO JENS

    IPC: G06F13/36 ,  G06F11/00 ,  G06F13/14 ,  G06F13/38 ,  G06F13/40

    Abstract: PROBLEM TO BE SOLVED: To provide an improved method and an execution system by which a buffer can be more effectively used in the case of transferring information between devices connected in an information processing system. SOLUTION: In this information processing system, a system bridge circuit can execute or over commits a transaction request from a system device to information transfer exceeding the current capacity of a bridge circuit in order to receive requested information while returning it from an instructed target device such as system memory 1O9 or other system device.

    DUAL HOST BRIDGE WITH PEER-TO-PEER SUPPORT
    4.
    发明专利
    DUAL HOST BRIDGE WITH PEER-TO-PEER SUPPORT 失效

    公开(公告)号：JPH1049482A

    公开(公告)日：1998-02-20

    申请号：JP8420597

    申请日：1997-04-02

    Applicant: IBM

    Inventor： GUTHRIE GUY LYNN ,  KELLEY RICHARD ALLEN ,  NEAL DANNY MARVIN ,  THURBER STEVE MARK

    IPC: G06F13/36 ,  G06F13/40

    Abstract: PROBLEM TO BE SOLVED: To efficiently process mixed transactions by connecting a 1st secondary bus and a 2nd secondary bus and connecting a bridge to a system bus which generates one logical bus supporting more peripheral devices than a previously set number. SOLUTION: A system 10 connects one host processor 12 to the 1st secondary bus 14 like a system bus that supports many peripheral devices which can be used by a multiprocessor system and also connects the other host processor 12 to the 1st secondary bus 14. Then the host bridge 20A is connected to the 1st secondary bus 14 and the 1st secondary bus 14 and 2nd secondary bus 16 are connected to each other. Further, a system memory 15 is connected to the 1st secondary bus 14 and 30 and 40 as other devices are connected to the 2nd secondary bus 16. Consequently, mixed transactions of the host bridge 20A can efficiently be processed.

    DMA WINDOW FOR LPAR ENVIRONMENT FOR ENABLING A PLURALITY OF IOA FOR ONE TERMINAL BRIDGE BY USING DEVICE ARBITRATION LEVEL
    5.
    发明专利
    DMA WINDOW FOR LPAR ENVIRONMENT FOR ENABLING A PLURALITY OF IOA FOR ONE TERMINAL BRIDGE BY USING DEVICE ARBITRATION LEVEL 审中-公开

    公开(公告)号：JP2002318701A

    公开(公告)日：2002-10-31

    申请号：JP2002010686

    申请日：2002-01-18

    Applicant: IBM

    Inventor： ARNDT RICHARD LOUIS ,  NEAL DANNY MARVIN ,  THURBER STEVE MARK

    IPC: G06F12/14 ,  G06F9/46 ,  G06F13/36 ,  G06F15/177

    Abstract: PROBLEM TO BE SOLVED: To prevent an I/O, which is to be used by one OS within a logically divided system, from destroying or fetching data belonging to the other OS within the system. SOLUTION: A hypervisor assigns an I/O bus direct memory access(DMA) address range to each of input/output adapters and prevents data from being transmitted between the input/output adapter inside one logic domain and a memory location assigned to the other logic domain during DMA operation. The I/O adapter(IOA) is connected through a terminal bridge to a PCI host bridge. A single terminal bridge can support a plurality of IOA as well, every terminal bridge has a plurality of sets of range registers, and each of sets is related to each of IOA. An arbiter is provided for selecting one of input/output adapters to use a PCI bus. The terminal bridge investigates a grant signal from the arbiter to the IOA and the set of range registers to be used is determined.

    BUS ARBITER WITH REINFORCED FUNCTION USING VARIABLE PRIORITY AND FAIRNESS
    6.
    发明专利
    BUS ARBITER WITH REINFORCED FUNCTION USING VARIABLE PRIORITY AND FAIRNESS 失效

    公开(公告)号：JP2001075918A

    公开(公告)日：2001-03-23

    申请号：JP2000228134

    申请日：2000-07-28

    Applicant: IBM

    Inventor： RICHARD ALLEN KELLY ,  NEAL DANNY MARVIN ,  THURBER STEVE MARK

    IPC: G06F13/36 ,  G06F13/362 ,  G06F13/364 ,  G06F13/40

    Abstract: PROBLEM TO BE SOLVED: To change arbitration priority levels by making a bus arbiter include logic in which a fairness system is embedded. SOLUTION: When a plurality of devices simultaneously request a bus, this bus arbiter resets all the bits of a fairness register to zero and starts a fairness protocol sequence. The bus arbiter deasserts all currently asserted enabling signals. Then, the bus arbiter asserts an enabling signal to a request source which does not set 1 in a corresponding fairness register bit and has the highest priority. Subsequently, the bus arbiter uses fairness algorithm and asserts an enabling signal to a request source having the highest priority when there is another device to which a request signal is asserted and which sets 1 in a fairness bit.

    7.
    发明专利
    未知

    公开(公告)号：DE69736872T2

    公开(公告)日：2007-04-26

    申请号：DE69736872

    申请日：1997-03-20

    Applicant: IBM

    Inventor： GUTHRIE GUY LYNN ,  KELLEY RICHARD ALLEN ,  NEAL DANNY MARVIN ,  THURBER STEVE MARK

    IPC: G06F13/40 ,  G06F13/36

    Abstract: A data processing system 10 includes a processor 12, system memory 15 and a number of peripheral devices 401, 403, and one or more bridges 400 which may connect between the processor, memory and peripheral devices and other hosts or peripheral devices such as in a network. A bridge, such as a PCI host bridge, connects between a primary bus (e.g system bus) 14 and a secondary bus 16. The host bridge 400 provides a dual host bridge function which creates two secondary bus interfaces. This allows increased loading capability under one dual host bridge compared to a lesser number of slots allowed under one normal host bridge. Also included is additional control logic for providing arbitration control and for steering transactions to the appropriate bus interface. Additionally, peer to peer support across the two secondary bus interfaces is provided.

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