Gating circuit for displaced pulses
    1.
    发明授权
    Gating circuit for displaced pulses 失效
    用于位移脉冲的加注电路

    公开(公告)号:US3567960A

    公开(公告)日:1971-03-02

    申请号:US3567960D

    申请日:1968-06-04

    Applicant: IBM

    CPC classification number: G11B20/1419 H03K5/00

    Abstract: A gating circuit useful for separating data pulses from clock pulses in a double frequency detection system includes a signal generator that provides a sawtooth waveform having ramp portions of the same slope and a flyback interval of fixed magnitude. When the sawtooth signal is above a variable threshold, an input gate is enabled to allow the clock pulses to initiate flyback. The proportions of the sawtooth waveform above and below the threshold remain constant, so that early or late arrival of a clock pulse does not affect the gating of succeeding clock pulses. Thus, an output gate is made to operate to block clock pulses while passing data pulses.

    3.
    发明专利
    未知

    公开(公告)号:FR2326756A1

    公开(公告)日:1977-04-29

    申请号:FR7625015

    申请日:1976-08-10

    Applicant: IBM

    Abstract: 1473772 Controlling light INTERNATIONAL BUSINESS MACHINES CORP 30 Sept 1975 39872/75 Heading G2F [Also in Division G5] In a display device comprising a transfer electrode El, a dump electrode E2 and a plurality of display electrode E3 immersed in a liquid electrolyte, a potential difference is first applied between electrodes E1 and E2 such as to deposit coloured material on E1, and subsequently a potential difference is applied between E1 and at least one electrode E3 so as effectively to transfer the coloured material to the selected electrode(s) E3. In Fig. 2, dot electrodes E3 are arranged in rows and columns, each column having a respective electrode E1 and E2 and the electrolyte being separated from that in adjacent columns by partitions 14 or by being contained in channels in a substrate. If the coloured material is such as to deposit at a cathode, it is initially deposited on selected electrode E1 by earthing the conductor 15 (FET 18, input T2) and by turning on selected FETs 19 to render corresponding electrode E2 positive. FETs 19 are controlled by a like array of bi-stables 23 forming an input/output register 24, AND gate 22 and control input Cl applied simultaneously with input T2. Subsequently an input T1 renders conductor 15 positive and, in the previously selected columns only, the coloured material is effectively transferred to the electrodes E3 of a selected row by activating the corresponding row input R2 (row conductor to earth). By repeating the process the array is scanned row sequentially. Non-linear resistances Z, e.g. oppositely poled diodes connected in parallel, are preferably provided between each electrode E1 and E3 and its row conductor. Erasure of the display is by turning on FETs 21 (input C2) and successively energizing terminals R1, or by short-circuiting the electrodes E3 to the dump electrode E2. The former erasure method may be used when the display requires refreshing to overcome dissipation of the coloured material by diffusion effects. The current between an electrode E2 and a coloured electrode E3 causes a current sense amplifier 27 to set the respective bi-stable 23 for a subsequent re-writing step. Partial or complete erasure of the display due to electrical read-out thereof may be counteracted similarly by applying sequential positive and negative current pulses across electrodes E2 and E3, the nett current being zero. During the positive pulse, terminal 29 is energized and the current between a written electrode and the electrode E2 produces an output from the amplifier 27, so that the following negative pulse restores the electrode E3 to its original written state. The device may also be constructed as a seven segment display.

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