公开(公告)号：US3576544A

公开(公告)日：1971-04-27

申请号：US3576544D

申请日：1968-10-18

Applicant: IBM

Inventor： CORDERO HUMBERTO JR ,  DRIMAK EDWARD G ,  PERKINS CHARLES B JR

IPC: G06F12/14 ,  G06F11/10 ,  G08B29/00

CPC classification number: G06F12/1466

Abstract: A system for protecting data in storage against inadvertent alteration. An access to main storage is preceded by an access to auxiliary storage. A portion of the auxiliary storage address is used to address a local storage unit for a protection key. When main storage is accessed, a portion of the main storage address is used to address the local storage unit for a storage key relating to the addressed area in main storage. The keys are compared and alteration of data at the main storage address is prevented if the keys do not match.

公开(公告)号：CA888407A

公开(公告)日：1971-12-14

申请号：CA888407D

Applicant: IBM

Inventor： CORDERO HUMBERTO JR ,  DRIMAK EDWARD G ,  PERKINS CHARLES B JR

公开(公告)号：FI46568B

公开(公告)日：1973-01-02

申请号：FI83165

申请日：1965-04-06

Applicant: IBM

Inventor： AMDAHL GENE M ,  BLAAUW GERRIT A ,  BOEHM ELAINE M ,  CALINGAERT PETER ,  CARNEVALE RICHARD J ,  CASE RICHARD PAUL ,  COLLINS ARTHUR F ,  GREENE JACK E ,  HANF WILLIAM P ,  JOHNSON JACOB R ,  MAGDALL ALBERT A ,  PERKINS CHARLES B JR ,  ROOD JOHN W ,  UPDIKE BRUCE M ,  VILLANTE ANTHONY E ,  WEBER HELMUT

IPC: G06F3/00 ,  G06F3/06 ,  G06F3/12 ,  G06F7/38 ,  G06F7/50 ,  G06F7/575 ,  G06F9/22 ,  G06F9/26 ,  G06F9/30 ,  G06F9/302 ,  G06F9/32 ,  G06F9/46 ,  G06F11/16 ,  G06F12/14 ,  G06F13/00 ,  G06F13/12 ,  G06F13/22 ,  G06F13/26 ,  G06F13/38 ,  G06F15/78 ,  G06F17/21 ,  G06F7/32

公开(公告)号：BR8704624A

公开(公告)日：1988-04-26

申请号：BR8704624

申请日：1987-09-04

Applicant: IBM

Inventor： BOURKE DONALD G ,  CHISHOLM DOUGLAS R ,  FLOAT GREGORY D ,  KELLEY RICHARD A ,  LIU ROY Y ,  MALMQUIST CARL A ,  NELSON JOHN M ,  PERKINS CHARLES B JR ,  PLACE RICHARD L ,  SCHWERMER HARTMUT R ,  WILSON JOHN DAVID

IPC: G06F13/36 ,  G06F13/40 ,  G06F13/20

Abstract: In a data processing system, an input output bus unit (IOBU) is connected to one end of an input output interface controller (IOIC) via an asynchronous bus. The other end of the IOIC is connected to a storage controller (SC) and an input output interface unit (IOIU) via a synchronous bus. The SC and IOIU are connected to a memory unit and an instruction processing unit. The asynchronous bus, which is comprised of three sub-buses and a control bus, conducts signals between the IOIC and an IOBU in an asynchronous "handshaking" manner. The synchronous bus, which is comprised of two sub-buses and a control bus, conducts signals between the IOIC and the SC/IOIU in an synchronous manner. The IOIC, interconnected between the synchronous bus and asynchronous bus, functions as a buffer between the faster synchronous bus and the slower asynchronous bus. Various operations are performed between an IOBU and the memory unit via the asynchronous bus, IOIC, synchronous bus, and SC/IOIU, such as a unit operation, a storage operation, and a message acceptance operation.

公开(公告)号：CA878146A

公开(公告)日：1971-08-10

申请号：CA878146D

Applicant: IBM

Inventor： ROOD JOHN W ,  WEBER HELMUT ,  CARNEVALE RICHARD J ,  UPDIKE BRUCE M ,  MAGDALL ALBERT A ,  BOEHM ELAINE M ,  CASE RICHARD P ,  GREENE JACK E ,  COLLINS ARTHUR F ,  PERKINS CHARLES B JR ,  AMDAHL GENE M ,  BLAAUW GERRIT A ,  VILLANTE ANTHONY E ,  JOHNSON JACOB R ,  HANF WILLIAM P ,  CALINGAERT PETER