公开(公告)号：JP2001308100A

公开(公告)日：2001-11-02

申请号：JP2001077127

申请日：2001-03-16

Applicant: IBM

Inventor： ELLIS-MONAGHAN JOHN J ,  FEENEY PAUL M ,  ROBERT M JEFFKEN ,  LANDIS HOWARD S ,  PREVITI-KELLY ROSEMARY A ,  BERGMAN-REUTER BETTE L ,  RUTTEN MATTHEW J ,  STAMPER ANTHONY K ,  YANKEE SALLY J

IPC: H01L23/52 ,  H01L21/3205 ,  H01L21/60 ,  H01L21/768 ,  H01L23/31 ,  H01L23/485 ,  H01L23/532

Abstract: PROBLEM TO BE SOLVED: To provide means for making an ultra-low k dielectric material which is compatible with a C4/wire bond structure. SOLUTION: The manufacturing method and structure of a semiconductor chip comprises a plurality of interconnecting metallization layers, at least one deformable dielectric material layer covering the interconnecting metallization layers, at least one I/O bonding pad, and a support structure including a fairly rigid dielectric in supporting relation with the pads and avoiding crushing of the deformable dielectric material layer.

公开(公告)号：JPH11191676A

公开(公告)日：1999-07-13

申请号：JP27270098

申请日：1998-09-28

Applicant: IBM

Inventor： JAMES M E HARPER ,  ROBERT M JEFFKEN

IPC: H05K3/46 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: PROBLEM TO BE SOLVED: To provide a multilayered interconnecting electronic component which is prolonged in electromigration life. SOLUTION: Interconnection is made into a stub form, and a vertical sidewall provided with a heat-resistant metal diffused barrier linear 15 which extends along it is included. A stub 14 has no barrier layer at the bottom, and the bottom of the stud 14 is brought into contact with a metal coating 12 on the dielectric layer 11 of a part. A continuos or discontinuous adhesive layer is provided between the bottom of the stud 14 and the surface of the metal coating 12. It is preferable that the adhesive layer be formed of a metal such as aluminum or the like which melts down in the stud 14 or the metal coating 12, when a part is heated during its formation or use. A suitable component employs a dual damask structure.

公开(公告)号：JP2004228569A

公开(公告)日：2004-08-12

申请号：JP2004003456

申请日：2004-01-08

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： COONEY III EDWARD C ,  ROBERT M JEFFKEN ,  MCGAHAY VINCENT J ,  MOTSIFF WILLIAM T ,  MURRAY MARK P ,  PIPER AMANDA L ,  STAMPER ANTHONY K ,  THOMAS DAVID C ,  TYBERG CHRISTY S ,  WEBSTER ELIZABETH T

IPC: H01L21/3205 ,  H01L21/768 ,  H01L21/82 ,  H01L23/52 ,  H01L23/522 ,  H01L23/525 ,  H01L23/532

CPC classification number: H01L21/76808 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76892 ,  H01L23/525 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1031 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide re-work processing methods of both the level of a single chip connecting or an interconnecting metal and a multilevel. SOLUTION: The method of re-working a BEOL (a back end of a process line) metallization levels of damascene metallurgy comprises the processes of: forming a plurality of BEOL metallization levels 101, 102 on a substrate 110; forming line and via portions in the BEOL metallization level; exposing the line section and the via section by selectively removing at least one BEOL metallization level; and replacing a removed BEOL metallization level with at least one of new BEOL metallization levels. The BEOL metallization levels 101, 102 comprises a first dielectric layers 120, 130 and second dielectric layers 125, 135, and the first dielectric layer includes a material having a dielectric constant lower than that of the second dielectric layer. COPYRIGHT: (C)2004,JPO&NCIPI

Abstract translation: 要解决的问题：提供单芯片连接或互连金属和多层的水平的再加工处理方法。 解决方案：重新加工大马士革冶金的BEOL（工艺线的后端）金属化水平的方法包括以下过程：在衬底110上形成多个BEOL金属化水平101,102; 在BEOL金属化水平上形成线和通孔部分; 通过选择性地去除至少一个BEOL金属化水平来暴露线段和通路部分; 并用至少一个新的BEOL金属化水平替换去除的BEOL金属化水平。 BEOL金属化层101,102包括第一电介质层120,130和第二电介质层125,135，并且第一电介质层包括介电常数低于第二电介质层的介电常数的材料。 版权所有（C）2004，JPO＆NCIPI

公开(公告)号：JP2001313371A

公开(公告)日：2001-11-09

申请号：JP2001073042

申请日：2001-03-14

Applicant: IBM

Inventor： ROBERT M JEFFKEN ,  STAMPER ANTHONY K

IPC: H01L21/3205 ,  H01L21/02 ,  H01L21/768 ,  H01L21/822 ,  H01L23/522 ,  H01L27/04

Abstract: PROBLEM TO BE SOLVED: To provide a metallic capacitor which is provided inside a metal layer on a semiconductor chip. SOLUTION: A lower plate of a capacitor is provided between an insulation layer and a dielectric layer. An insulation layer is disposed adjacent to a metallization layer, and a dielectric layer separates a lower plate of a capacitor from the upper plate of the capacitor. The shoulder part of a lower plate is adjacent to it and brought into contact with a via filled with copper. Although a via extends upward to a common surface of the upper plate, it is electrically isolated from an upper plate. A via also extends downward toward a metallization layer. This structure is formed by a copper dual-damascene process.