公开(公告)号：EP1846851A4

公开(公告)日：2009-11-04

申请号：EP05854489

申请日：2005-12-16

Applicant: IBM

Inventor： LANDIS HOWARD S

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

公开(公告)号：JP2001308100A

公开(公告)日：2001-11-02

申请号：JP2001077127

申请日：2001-03-16

Applicant: IBM

Inventor： ELLIS-MONAGHAN JOHN J ,  FEENEY PAUL M ,  ROBERT M JEFFKEN ,  LANDIS HOWARD S ,  PREVITI-KELLY ROSEMARY A ,  BERGMAN-REUTER BETTE L ,  RUTTEN MATTHEW J ,  STAMPER ANTHONY K ,  YANKEE SALLY J

IPC: H01L23/52 ,  H01L21/3205 ,  H01L21/60 ,  H01L21/768 ,  H01L23/31 ,  H01L23/485 ,  H01L23/532

Abstract: PROBLEM TO BE SOLVED: To provide means for making an ultra-low k dielectric material which is compatible with a C4/wire bond structure. SOLUTION: The manufacturing method and structure of a semiconductor chip comprises a plurality of interconnecting metallization layers, at least one deformable dielectric material layer covering the interconnecting metallization layers, at least one I/O bonding pad, and a support structure including a fairly rigid dielectric in supporting relation with the pads and avoiding crushing of the deformable dielectric material layer.

公开(公告)号：WO2008100915A3

公开(公告)日：2008-10-09

申请号：PCT/US2008053694

申请日：2008-02-12

Applicant: IBM ,  KUMAR AMIT ,  LANDIS HOWARD S ,  SUCHARITAVES JEANNE-TANIA

Inventor： KUMAR AMIT ,  LANDIS HOWARD S ,  SUCHARITAVES JEANNE-TANIA

IPC: G06F17/50

CPC classification number: G03F1/36

Abstract: Structures and methods for forming the same. The method (200) includes providing design information of a design layer (100a). The design layer (100a) includes M original design features (140) and N original dummy features (150). The method further includes (i) creating a cluster (300) of P representative dummy features (310), P being a positive integer less than N, (ii) performing OPC for the cluster of the P representative dummy features (310) but not for the N original dummy features (150), resulting in P OPC-applied representative dummy features (320), and (iii) forming the mask including N mask dummy features. The N mask dummy features are identical. Each mask dummy feature of the N mask dummy features of the mask has an area which is a function of at least an area of an OPC-applied representative dummy feature (320) of the P OPC-applied representative dummy features (320). The N mask dummy features have the same relative positions as the N original dummy feature (150).

Abstract translation: 用于形成它的结构和方法。 方法（200）包括提供设计层（100a）的设计信息。 设计层（100a）包括M个原始设计特征（140）和N个原始虚拟特征（150）。 该方法还包括（i）创建P代表虚拟特征（310）的簇（300），P是小于N的正整数，（ii）对P代表虚拟特征（310）的簇执行OPC，但不 对于N个原始虚拟特征（150），导致P OPC应用的代表虚拟特征（320），以及（iii）形成包括N个掩码虚拟特征的掩码。 N个掩码虚拟特征是相同的。 掩模的N个掩模虚拟特征的每个掩码虚拟特征具有至少是P OPC应用的代表虚拟特征（320）中的OPC应用的代表性虚拟特征（320）的区域的函数的区域。 N掩模伪特征具有与N原始伪特征（150）相同的相对位置。

公开(公告)号：WO2006073758A3

公开(公告)日：2007-03-01

申请号：PCT/US2005045787

申请日：2005-12-16

Applicant: IBM ,  LANDIS HOWARD S

Inventor： LANDIS HOWARD S

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

Abstract: Methods, systems, program products are disclosed that control placement of dummy shapes (200) about sensitive circuit elements (172) such that the dummy shapes are at least substantially similar for each circuit element even though the dummy shapes are auto-generated. In one embodiment, the invention includes providing dummy shape pattern pitch information (XP, YP) to a designer, and allowing placement of circuit elements at integer multiples of one or more of the pitches such that the dummy shapes are at least substantially similar about each instance of the circuit element. Another embodiment includes allowing placement of a marker (300) about a circuit element (372) to indicate an area in which dummy shapes (306) are to be substantially identical, and then using the marker to place the circuit element. Dummy shapes generated within the marker ensure substantially identical dummy shapes for each instance of the circuit element. The invention also includes the integrated circuits formed.

Abstract translation: 公开了方法，系统，程序产品，其控制关于敏感电路元件（172）的虚拟形状（200）的放置，使得即使虚拟形状被自动生成，虚拟形状对于每个电路元件至少基本相似。 在一个实施例中，本发明包括向设计者提供虚拟形状图案间距信息（XP，YP），并允许将电路元件放置在一个或多个间距的整数倍处，使得虚拟形状至少基本上相似于每个 电路元件的实例。 另一个实施例包括允许围绕电路元件（372）放置标记（300）以指示虚拟形状（306）基本上相同的区域，然后使用标记来放置电路元件。 在标记内产生的虚拟形状确保电路元件的每个实例基本相同的虚拟形状。 本发明还包括形成的集成电路。

公开(公告)号：DE10110566B4

公开(公告)日：2007-03-01

申请号：DE10110566

申请日：2001-03-06

Applicant: IBM

Inventor： ELLIS-MONAGHAN JOHN J ,  FEENEY PAUL M ,  GEFFKEN ROBERT M ,  LANDIS HOWARD S ,  PREVITI-KELLY ROSEMARY A ,  BERGMAN-REUTER BETTE L ,  RUTTEN MATTHEW J ,  STAMPER ANTHONY K ,  YANKEE SALLY J

IPC: H01L23/50 ,  H01L23/52 ,  H01L21/312 ,  H01L21/314 ,  H01L21/3205 ,  H01L21/60 ,  H01L21/768 ,  H01L23/31 ,  H01L23/485 ,  H01L23/532

Abstract: A method and structure for a semiconductor chip includes a plurality of layers of interconnect metallurgy, at least one layer of deformable dielectric material over the interconnect metallurgy, at least one input/output bonding pad, and a support structure that includes a substantially rigid dielectric in a supporting relationship to the pad that avoids crushing the deformable dielectric material.

公开(公告)号：MY117703A

公开(公告)日：2004-07-31

申请号：MYPI20010672

申请日：2001-02-14

Applicant: IBM

Inventor： ELLIS-MONAGHAN JOHN J ,  FEENEY PAUL M ,  GEFFKEN ROBERT M ,  LANDIS HOWARD S ,  PREVITI-KELLY ROSEMARY A ,  REUTER BETTE BERGMAN L ,  RUTTEN MATTHEW J ,  STAMPER ANTHONY K ,  YANKEE SALLY J

IPC: H01L23/52 ,  H01L23/58 ,  H01L21/3205 ,  H01L21/60 ,  H01L21/768 ,  H01L23/31 ,  H01L23/485 ,  H01L23/532

Abstract: A METHOD AND STRUCTURE FOR A SEMICONDUCTOR CHIP INCLUDES A PLURALITY OF LAYERS OF INTERCONNECT METALLURGY, AT LEAST ONE LAYER OF DEFORMABLE DIELECTRIC MATERIAL OVER THE INTERCONNECT METALLURGY, AT LEAST ONE INPUT/OUTPUT BONDING PAD, AND A SUPPORT STRUCTURE THAT INCLUDES A SUBSTANTIALLY RIGID DIELECTRIC IN A SUPPORTING RELATIONSHIP TO THE PAD THAT AVOIDS CRUSHING THE DEFORMABLE DIELECTRIC MATERIAL.

公开(公告)号：DE10110566A1

公开(公告)日：2001-09-27

申请号：DE10110566

申请日：2001-03-06

Applicant: IBM

Inventor： ELLIS-MONAGHAN JOHN J ,  FEENEY PAUL M ,  GEFFKEN ROBERT M ,  LANDIS HOWARD S ,  PREVITI-KELLY ROSEMARY A ,  BERGMAN-REUTER BETTE L ,  RUTTEN MATTHEW J ,  STAMPER ANTHONY K ,  YANKEE SALLY J

IPC: H01L23/52 ,  H01L21/3205 ,  H01L21/60 ,  H01L21/768 ,  H01L23/31 ,  H01L23/485 ,  H01L23/532 ,  H01L23/50 ,  H01L21/314

Abstract: Over the coupling metallising is deposited at least one film of deformable dielectric material. A support structure, contg. rigid dielectric, is connected to the deformable dielectric and to an input-output bond island.The support structure also supports the bond island to prevent the fracture of the deformable dielectric material. Typically the support structure contains a cap over the deformable dielectric material, coplanar with the structured last metallising layer. Independent claims are included for integrated circuit chip and for mfr. of semiconductor chip.