公开(公告)号：JP2001308100A

公开(公告)日：2001-11-02

申请号：JP2001077127

申请日：2001-03-16

Applicant: IBM

Inventor： ELLIS-MONAGHAN JOHN J ,  FEENEY PAUL M ,  ROBERT M JEFFKEN ,  LANDIS HOWARD S ,  PREVITI-KELLY ROSEMARY A ,  BERGMAN-REUTER BETTE L ,  RUTTEN MATTHEW J ,  STAMPER ANTHONY K ,  YANKEE SALLY J

IPC: H01L23/52 ,  H01L21/3205 ,  H01L21/60 ,  H01L21/768 ,  H01L23/31 ,  H01L23/485 ,  H01L23/532

Abstract: PROBLEM TO BE SOLVED: To provide means for making an ultra-low k dielectric material which is compatible with a C4/wire bond structure. SOLUTION: The manufacturing method and structure of a semiconductor chip comprises a plurality of interconnecting metallization layers, at least one deformable dielectric material layer covering the interconnecting metallization layers, at least one I/O bonding pad, and a support structure including a fairly rigid dielectric in supporting relation with the pads and avoiding crushing of the deformable dielectric material layer.

公开(公告)号：DE10110566B4

公开(公告)日：2007-03-01

申请号：DE10110566

申请日：2001-03-06

Applicant: IBM

Inventor： ELLIS-MONAGHAN JOHN J ,  FEENEY PAUL M ,  GEFFKEN ROBERT M ,  LANDIS HOWARD S ,  PREVITI-KELLY ROSEMARY A ,  BERGMAN-REUTER BETTE L ,  RUTTEN MATTHEW J ,  STAMPER ANTHONY K ,  YANKEE SALLY J

IPC: H01L23/50 ,  H01L23/52 ,  H01L21/312 ,  H01L21/314 ,  H01L21/3205 ,  H01L21/60 ,  H01L21/768 ,  H01L23/31 ,  H01L23/485 ,  H01L23/532

Abstract: A method and structure for a semiconductor chip includes a plurality of layers of interconnect metallurgy, at least one layer of deformable dielectric material over the interconnect metallurgy, at least one input/output bonding pad, and a support structure that includes a substantially rigid dielectric in a supporting relationship to the pad that avoids crushing the deformable dielectric material.

公开(公告)号：MY117703A

公开(公告)日：2004-07-31

申请号：MYPI20010672

申请日：2001-02-14

Applicant: IBM

Inventor： ELLIS-MONAGHAN JOHN J ,  FEENEY PAUL M ,  GEFFKEN ROBERT M ,  LANDIS HOWARD S ,  PREVITI-KELLY ROSEMARY A ,  REUTER BETTE BERGMAN L ,  RUTTEN MATTHEW J ,  STAMPER ANTHONY K ,  YANKEE SALLY J

IPC: H01L23/52 ,  H01L23/58 ,  H01L21/3205 ,  H01L21/60 ,  H01L21/768 ,  H01L23/31 ,  H01L23/485 ,  H01L23/532

Abstract: A METHOD AND STRUCTURE FOR A SEMICONDUCTOR CHIP INCLUDES A PLURALITY OF LAYERS OF INTERCONNECT METALLURGY, AT LEAST ONE LAYER OF DEFORMABLE DIELECTRIC MATERIAL OVER THE INTERCONNECT METALLURGY, AT LEAST ONE INPUT/OUTPUT BONDING PAD, AND A SUPPORT STRUCTURE THAT INCLUDES A SUBSTANTIALLY RIGID DIELECTRIC IN A SUPPORTING RELATIONSHIP TO THE PAD THAT AVOIDS CRUSHING THE DEFORMABLE DIELECTRIC MATERIAL.

公开(公告)号：DE10110566A1

公开(公告)日：2001-09-27

申请号：DE10110566

申请日：2001-03-06

Applicant: IBM

Inventor： ELLIS-MONAGHAN JOHN J ,  FEENEY PAUL M ,  GEFFKEN ROBERT M ,  LANDIS HOWARD S ,  PREVITI-KELLY ROSEMARY A ,  BERGMAN-REUTER BETTE L ,  RUTTEN MATTHEW J ,  STAMPER ANTHONY K ,  YANKEE SALLY J

IPC: H01L23/52 ,  H01L21/3205 ,  H01L21/60 ,  H01L21/768 ,  H01L23/31 ,  H01L23/485 ,  H01L23/532 ,  H01L23/50 ,  H01L21/314

Abstract: Over the coupling metallising is deposited at least one film of deformable dielectric material. A support structure, contg. rigid dielectric, is connected to the deformable dielectric and to an input-output bond island.The support structure also supports the bond island to prevent the fracture of the deformable dielectric material. Typically the support structure contains a cap over the deformable dielectric material, coplanar with the structured last metallising layer. Independent claims are included for integrated circuit chip and for mfr. of semiconductor chip.