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    METHOD FOR FORMING SELF-ALIGNED DUAL SALICIDE IN CMOS TECHNOLOGIES
    1.
    发明公开
    METHOD FOR FORMING SELF-ALIGNED DUAL SALICIDE IN CMOS TECHNOLOGIES 审中-公开
    方法形成自对准DOPPELSALIZID CMOS技术

    公开(公告)号：EP1825508A4

    公开(公告)日：2009-06-24

    申请号：EP05852638

    申请日：2005-12-01

    Applicant: IBM

    Inventor： CABRAL CYRIL JR ,  DZIOBKOWSKI CHESTER T ,  ELLIS-MONAGHAN JOHN J ,  FANG SUNFEI ,  LAVOIE CHRISTIAN ,  LUO ZHIJIONG ,  NAKOS JAMES S ,  STEEGEN AN L ,  WANN CLEMENT H

    IPC: H01L21/8238 ,  H01L21/3205 ,  H01L21/44 ,  H01L21/4763

    CPC classification number: H01L21/28518 ,  H01L21/823814 ,  H01L21/823835

    Abstract: A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region (103) in a semiconductor substrate (102) for accommodation of a first type semiconductor device (130); forming a second well region (104) in the semiconductor substrate (102) for accommodation of a second type semiconductor device (140); shielding the first type semiconductor device (130) with a mask (114); depositing a first metal layer (118) over the second type semiconductor device (140); performing a first salicide formation on the second type semiconductor device (140); removing the mask (114); depositing a second metal layer (123) over the first and second type semiconductor devices (130,140); and performing a second salicide formation on the first type semiconductor device (130). The method requires only one pattern level and it eliminates pattern overlay as it also simplifies the processes to form different suicide material over different devices.

    FIELD EFFECT TRANSISTOR AND FABRICATION THEREOF
    3.
    发明专利
    FIELD EFFECT TRANSISTOR AND FABRICATION THEREOF 失效

    公开(公告)号：JP2000101093A

    公开(公告)日：2000-04-07

    申请号：JP24211799

    申请日：1999-08-27

    Applicant: IBM

    Inventor： BRYANT ANDRES ,  CLARK WILLIAM F ,  ELLIS-MONAGHAN JOHN J ,  MACIEJEWSKI EDWARD P ,  EDWARD J NOWACK ,  WILBUR D PRISER ,  MIN H TONG

    IPC: H01L27/06 ,  H01L21/8234 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786

    Abstract: PROBLEM TO BE SOLVED: To provide a device structure of SOI(silicon on isulator) CMOS (complementary metal oxide semiconductor) in which avalanche multiplication of current flowing through a device is increased when an FET(field effect transistor) is turned on and body charges are removed when the FET is turned off. SOLUTION: An FET having an electric floating body is substantially isolated electrically from a substrate. A high resistance path 16 for coupling the floating body is provided at the source. The resistor is operated as a floating body for active switching and a body grounded in waiting mode in order to reduce leakage current. The high resistance path has a resistance of at least 1 MΩ and made of polysilicon. The resistor is formed using a split polysilicon process for opening a hole in a first polysilicon layer in order that an embedded contact mask 19 brings a second polysilicon layer into contact with the substrate.

    METHODS FOR FORMING ANTI-REFLECTION STRUCTURES FOR CMOS IMAGE SENSORS
    4.
    发明申请
    METHODS FOR FORMING ANTI-REFLECTION STRUCTURES FOR CMOS IMAGE SENSORS 审中-公开
    用于形成CMOS图像传感器的抗反射结构的方法

    公开(公告)号：WO2009140099A3

    公开(公告)日：2010-01-21

    申请号：PCT/US2009042766

    申请日：2009-05-05

    Applicant: IBM ,  ADKISSON JAMES W ,  ELLIS-MONAGHAN JOHN J ,  GAMBINO JEFFREY P ,  MUSANTE CHARLES F

    Inventor： ADKISSON JAMES W ,  ELLIS-MONAGHAN JOHN J ,  GAMBINO JEFFREY P ,  MUSANTE CHARLES F

    IPC: H01L31/112

    CPC classification number: H01L27/14685 ,  H01L27/14618 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/14632 ,  H01L27/14645 ,  H01L27/14689 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00

    Abstract: Protuberances (5), having vertical (h) and lateral (p) dimensions less than the wavelength range of lights detectable by a photodiode (8), are formed at an optical interface between two layers having different refractive indices. The protuberances may be formed by employing self-assembling block copolymers that form an array of sub lithographic features of a first polymeric block component (112) within a matrix of a second polymeric block component (111). The pattern of the polymeric block component is transferred into a first optical layer (4) to form an array of nanoscale protuberances. Alternately, conventional lithography may be employed to form protuberances having dimensions less than the wavelength of light. A second optical layer is formed directly on the protuberances of the first optical layer. The interface between the first and second optical layers has a graded refractive index, and provides high transmission of light with little reflection.

    Abstract translation: 具有小于由光电二极管（8）可检测的光的波长范围的垂直（h）和横向（p）尺寸的凸起（5）形成在具有不同折射率的两个层之间的光学界面处。 突起可以通过使用在第二聚合物嵌段组分（111）的基体内形成第一聚合物嵌段组分（112）的亚光刻特征阵列的自组装嵌段共聚物来形成。 聚合物嵌段组分的图案被转移到第一光学层（4）中以形成纳米级突起的阵列。 或者，可以使用常规光刻来形成尺寸小于光的波长的突起。 第二光学层直接形成在第一光学层的突起上。 第一和第二光学层之间的界面具有渐变的折射率，并提供很少的反射光的高透射率。

    SILICON-ON-INSULATOR (SOI) STRUCTURE CONFIGURED FOR REDUCED HARMONICS, DESIGN STRUCTURE AND METHOD
    5.
    发明申请
    SILICON-ON-INSULATOR (SOI) STRUCTURE CONFIGURED FOR REDUCED HARMONICS, DESIGN STRUCTURE AND METHOD 审中-公开
    用于降低谐波的硅绝缘体（SOI）结构，设计结构和方法

    公开(公告)号：WO2011066035A3

    公开(公告)日：2011-07-28

    申请号：PCT/US2010050805

    申请日：2010-09-30

    Applicant: IBM ,  BOTULA ALAN B ,  ELLIS-MONAGHAN JOHN J ,  JOSEPH ALVIN J ,  LEVY MAX G ,  PHELPS RICHARD A ,  SLINKMAN JAMES A

    Inventor： BOTULA ALAN B ,  ELLIS-MONAGHAN JOHN J ,  JOSEPH ALVIN J ,  LEVY MAX G ,  PHELPS RICHARD A ,  SLINKMAN JAMES A

    IPC: H01L27/12

    CPC classification number: H01L29/78603 ,  H01L21/84 ,  H01L27/1203

    Abstract: Disclosed is semiconductor structure (100) with an insulator layer (120) on a semiconductor substrate (110) and a device layer (130) is on the insulator layer. The substrate (110) is doped with a relatively low dose of a dopant (111) having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion (102) of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant (111), a different dopant (112) having the same conductivity type or a combination thereof (111 and 112). Optionally, micro-cavities (122, 123) are created within this same portion (102) so as to balance out any increase in conductivity with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method and a design structure for such a semiconductor structure.

    Abstract translation: 公开了在半导体衬底（110）上具有绝缘体层（120）并且器件层（130）位于绝缘体层上的半导体结构（100）。 衬底（110）掺杂有相对低剂量的具有给定导电类型的掺杂剂（111），使得其具有相对高的电阻率。 此外，紧邻绝缘体层的半导体衬底的一部分（102）可以用稍高剂量的相同掺杂剂（111），具有相同导电类型的不同掺杂剂（112）或其组合（111 和112）。 可选地，在该相同部分（102）内形成微腔（122,123），以平衡电导率的任何增加以及电阻率的相应增加。 增加半导体衬底 - 绝缘体层界面处的掺杂剂浓度提高了任何得到的寄生电容器的阈值电压（Vt），从而降低了谐波行为。 在此还公开了用于这种半导体结构的方法和设计结构的实施例。

    Selective nitriding of gate oxide film
    6.
    发明专利
    Selective nitriding of gate oxide film 有权
    栅极氧化膜的选择性硝化

    公开(公告)号：JP2005210123A

    公开(公告)日：2005-08-04

    申请号：JP2005011499

    申请日：2005-01-19

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： BURNHAM JAY S ,  ELLIS-MONAGHAN JOHN J ,  NAKOS JAMES S ,  QUINLIVAN JAMES J

    IPC: H01L27/092 ,  H01L21/318 ,  H01L21/8238 ,  H01L29/78

    CPC classification number: H01L21/823857

    Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor structure including a thin gate dielectric in which nitrogen is selectively enriched.
    SOLUTION: Although an introducing amount of nitrogen is sufficient to cause gate leakage and the infiltration of a dopant to be reduced, or to prevent these, the amount does not decrease device performance much. Nitrogen lower than that of a gate dielectric of nFET in density is introduced into a gate dielectric of a pFET. Nitriding can be selectively carried out by rapid thermal nitridation (RTN), furnace nitriding, remote plasma nitriding (RPN), decoupled plasma nitriding (DPN), and wale implantation or polysilicon implantation, or by various techniques, including combinations of these methods.
    COPYRIGHT: (C)2005,JPO&NCIPI

    Abstract translation: 解决的问题：提供一种包括选择性富集氮气的薄栅电介质的半导体结构。 解决方案：尽管氮的引入量足以导致栅极泄漏和掺杂剂的渗透减少，或者为了防止这些，但是量不会大大降低器件性能。 低于nFET的栅极电介质的密度的氮被引入pFET的栅极电介质中。 氮化可以通过快速热氮化（RTN），炉氮化，远程等离子体氮化（RPN），去耦等离子体氮化（DPN），纵行注入或多晶硅注入，或通过各种技术（包括这些方法的组合）来选择性地进行。 版权所有（C）2005，JPO＆NCIPI

    Method for forming semiconductor structure comprising different species of silicide/germanide with cmos technique
    9.
    发明专利
    Method for forming semiconductor structure comprising different species of silicide/germanide with cmos technique 审中-公开
    用CMOS技术形成含有硅酮/锗的不同物种的半导体结构的方法

    公开(公告)号：JP2007150293A

    公开(公告)日：2007-06-14

    申请号：JP2006303411

    申请日：2006-11-08

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： RIM KERN ,  ELLIS-MONAGHAN JOHN J ,  ROBERT J PURTELL ,  BRIAN J GREENE ,  CLEMENT H WANN ,  WILLIAM K HENSON ,  WILDMAN HORATIO S

    IPC: H01L21/28

    CPC classification number: H01L21/28518 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/84

    Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a semiconductor structure comprising different species of silicide or germanide positioned in different regions of the semiconductor structure.
    SOLUTION: The different species of silicide or germanide is formed on a semiconductor layer and/or a conductor layer. By this invention, by utilizing combination of continuous accumulation of different metals and pattern formation, the different silicide or germanide are formed in the different regions of a semiconductor chip. This method includes a step for providing a Si-including layer or a Ge layer having at least a first region and a second region, a step for forming a first silicide or germanide in one of the first region and the second region, and a step for forming a second silicide or germanide having different composition from the first silicide or germanide in the other region not including the first silicide or germanide. The steps for forming the first and second silicide or germanide are performed continuously or with a single step.
    COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种形成半导体结构的方法，所述半导体结构包括位于半导体结构的不同区域中的不同种类的硅化物或锗化物。 解决方案：在半导体层和/或导体层上形成不同种类的硅化物或锗化物。 通过本发明，通过利用不同金属的连续积累和图案形成的组合，在半导体芯片的不同区域中形成不同的硅化物或锗化物。 该方法包括提供具有至少第一区域和第二区域的含Si的层或Ge层的步骤，在第一区域和第二区域之一中形成第一硅化物或锗化物的步骤，以及步骤 用于在不包括第一硅化物或锗化锗的另一区域中形成具有不同组成的第二硅化物或锗化物与第一硅化物或锗化物。 用于形成第一和第二硅化物或锗化物的步骤连续地或单步进行。 版权所有（C）2007，JPO＆INPIT

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