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公开(公告)号：DE2530599A1
公开(公告)日：1976-01-29
申请号：DE2530599
申请日：1975-07-09
Applicant: IBM
Inventor： BODNER RONALD EUGENE , CROOKS THOMAS LEE , GUEST JOHN EDWARD , ROCHESTER MINN , MAGRISSO ISRAEL BEN , SLACK KEITH KENNETH
Abstract: Control circuitry in a computer system is responsive to an allow cycle steal signal from an I/O attachment operating in a burst or dedicated data transfer mode and generates control signals whereby the next data storage cycle is made available to an I/O device which is also capable of operating in a cycle steal mode. Upon completion of the next storage cycle, the operation reverts to burst mode and the I/O attachment operating in the burst mode is granted ensuing data storage cycles until it relinquishes a storage cycle to an I/O device capable of using and having a need for it.
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公开(公告)号：DE1524412A1
公开(公告)日：1971-04-01
申请号：DE1524412
申请日：1966-08-02
Applicant: IBM
Inventor： ANDREW GARRY GERALD , JAMES KOSTUCH DONALD , ROCHESTER MINN , WESLEY LAWLESS FREDERICK , LEE MALABY DAVEY
Abstract: 1,109,349. Line identification. INTERNATIONAL BUSINESS MACHINES CORPORATION. 25 July. 1966 [9 Aug., 1965], No. 3309/66. Heading G4R. Line identification apparatus detects coded line representations fixed with respect to a document which bears lines to be identified. Fig. 4 shows a document which bears lines of characters (not shown) to be scanned and read by a cathode ray tube (and photomultiplier),. Sets of coded indicia in a line identification track are provided to allow lines to be identified for subsequent marking when they contain unreadable characters, and to facilitate indexing of the document after one group of lines has been scanned to bring the next group into position. Each set of coded indicia is a set of horizontal bars 19 present or absent to represent 1 and 0 respectively. Thicker so-called bracket bars 17 separate successive sets of the coded indicia. Other bars are provided as shown. The document is advanced until a photodetector 33 has detected both bars 30 and 29 after which it is stopped. The beam of the cathode ray tube is then at 35. The beam is moved rightwards until it encounters bar 27 when it backs off and moves downwards to read coded indicia 26 (bars present and absent) identifying the document. When a predetermined distance below a bracket bar 28, the beam moves rightwards in a line searching raster to find a line of characters. On detecting a line, the raster is normalized and centred on it (no details) as it moves rightwards. When it reaches the right-hand end of the line it returns leftwards to read the characters (no details). If all the characters are read successfully, the beam moves downwards and rasters along the next line. However, if a character could not be read the beam crosses horizontally into the line identification track then moves upwards. During the upward movement until the first bracket bar is detected, a first counter (354, Fig 2e, not shown) counts clock pulses to give a fine component of the line position, this fine component then being transferred to latches (363- 368, Fig. 2e, not shown). The coded indicia detected until the next bracket bar is reached give a coarse component of the line position and are gated into latches (377-382, Fig. 2e, not shown) under control of the decoded (410) output of the first counter (354) now being fed with clock pulses for this purpose. The fine and coarse components are passed to a central processor store. The beam returns downwards along the same path (despite Fig. 4) and after it passes the lower bracket bar, the first counter (354) counts clock pulses until the count equals the latched fine component (363-368) as determined by AND gates (395-401, Fig. 2e, not shown) whereupon the beam moves rightwards to find another line of characters. For indexing the document, the coarse and fine components of the position of the last line to be scanned are obtained and latched as before, the coarse component being passed to further latches (389-394). The document is moved and bars 16, 17 detected at 39 are counted by a second counter (427, Fig. 2f, not shown) preset with the number of bars between the detector 39 and the required stop position. When the count equals the latched coarse component (389-394) as determined by AND gates (428-433, Fig. 2#, not shown), clock pulses are gated to the first counter (354, Fig. 2e, not shown) the count being compared (395-401) with the latched fine component (363-368) of the last line to be scanned prior to indexing. On equality, the document is stopped. The last line to be scanned prior to indexing is now identified by reading successive sets of the coded indicia during downward movement of the beam, latching them (377-382, Fig. 2e, not shown) and comparing them (402-107, Fig. 2f, not shown) with the coarse component (389-394) of said last line. On equality, beam movement continues with counting of clock pulses in the first counter (354, Fig. 2e, not shown) until the count equals (395-401) the fine component (363-368) of said last line. The beam then moves downwards and to the right to scan the next line of characters. Lines can be marked by printing in the line mark track 36 at another station while a further document is being read. As the document moves through the second station, a detector 67 detects the bars 16, 17 which are counted (475, Fig. 2b, not shown) the count being compared (476-482) with the coarse component of the position of the first line to be marked (from the central processor store). On equality, clock pulses are gated to a further counter (485, Fig. 2b, not shown) until the count equals (486-492) the fine component of the line position (from the central processor store) when the marker is actuated. Further lines are marked similarly. Modifications.-In a second embodiment, the document (Fig. 7, not shown) is similar except that thick and thin (rather than present and absent) bars are used to represent 1 and 0, and a bar (56) to stop the document initially is in the line identification track. An 8-bit shift register (515, Figs. 5c, 5g, not shown) is provided for receiving a 5-bit set of document or line identifying indicia (read during downward movement of the beam) and two 1-bits produced by two bracket bars bracketing the set. An AND gate (548, Fig. 5g, not shown) verifies that a valid code has been shifted in, viz. that the first and seventh stages hold 1 (the bracket bars) and the eighth holds 0, and a trigger (550, Fig. 5g, not shown) verifies that an odd number of bits have been shifted in. A fine component is obtained by counting (595, Fig. 5d, not shown) as before. Comparisons of fine component counts are done by entering the complement of the first into the last-mentioned counter (595) and incrementing to capacity. The line identification track could be on a belt or plate referenced with respect to the document, rather than on the document itself.
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公开(公告)号：DE2846624A1
公开(公告)日：1979-05-31
申请号：DE2846624
申请日：1978-10-26
Applicant: IBM
Abstract: Analog voltage levels derived from optically scanning a document or from magnetically scanning a magnetic record, depend upon the variable amplitude of a background signal. The analog voltage levels are processed by a bucket brigade circuit to set a threshold from which a binary decision may be made as to the presence of a black or white indicium in optical recognition or a one (1) or zero (0) bit in magnetic reading.
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公开(公告)号：DE2452798A1
公开(公告)日：1975-05-22
申请号：DE2452798
申请日：1974-11-07
Applicant: IBM
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公开(公告)号：DE2228141A1
公开(公告)日：1973-01-11
申请号：DE2228141
申请日：1972-06-09
Applicant: IBM
Inventor： JENSEN DONALD FREDERICK , LAGERGREN RICHARD EDWARD , LENTZ ROBERT CHARLES , REIDENBACH JOHN RALPH , ROCHESTER MINN , SCHAFFER ROBERT RUDOLPH
IPC: G06K7/02 , H01L23/29 , H01L23/522
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Patent Agency Ranking
公开(公告)号：DE1774896B1
公开(公告)日：1972-05-31
申请号：DE1774896
申请日：1968-09-27
Applicant: IBM
Inventor： ALLEN BELL KENNETH , JOSEPH KLATZ RAYMOND , ROCHESTER MINN , EARL WALLIS DONALD , KAY WOMACK KARL
Abstract: 1,233,951. Data processing. INTERNATIONAL BUSINESS MACHINES CORP. 23 Aug., 1968 [27 Sept., 1967], No. 40417/68. Heading G4A. A data processing system comprises a main store for data and control words, an auxiliary store capable of performing a plurality of read/ write cycles during each read/write cycle of the main store, means to read out a multi-byte word from the main store and selective transfer means to transfer a multi-byte data word to the auxiliary store or a multi-byte control word to a control register, means to send a data word in the auxiliary store a byte at a time to an arithmetic logic unit for processing and to store the result in the auxiliary store, a control word being read from the main store to a control register and decoded to provide a sequence of control signals to control the processing of one byte from at least one data word by the arithmetic logic unit. The main store also stores instruction words. The auxiliary ("active") store has predetermined locations for the instruction counter, main store addresses of two operands, working areas and general purpose registers. Each operand address from the auxiliary store has a word portion for addressing the main store to obtain a (4-byte) operand word which is then stored in one of the auxiliary store working areas. The operand address also has a 2-bit byte portion indicating the first byte of the operand word which actually belongs to this operand. The byte portion is stored in a marker register in a sub-unit accessing and modifier circuit. The marker register has space for two such byte portions (for two operands respectively), and a 4-bit mask which is set as successive bytes are processed to indicate which bytes of the appropriate one of the main store operand words are to be replaced by the processing result when this is transferred into the main store from the auxiliary store. As successive bytes are processed the byte address portions in the marker register are incremented or decremented (according as bytes are taken going rightwards or leftwards along the operand words) by two 2-bit parallel adders which also function as decoders and serve to select, from operand words read from the auxiliary store, successive bytes to be fed to the arithmetic logic unit, and serve to update the mask in the marker register. Control words, besides feeding the control register, the contents of which are decoded to control system operation, also go direct to further decoding circuits, some of which control the main store to read or write a byte, half-word or word, selectively, the information read or written going to or coming from the auxiliary store. Control words also control addressing of the auxiliary store.
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公开(公告)号：DE2556624A1
公开(公告)日：1976-07-08
申请号：DE2556624
申请日：1975-12-16
Applicant: IBM
Inventor： BODNER RONALD EUGENE , CIANCIOSI MARIO NICHOLAS , CROOKS THOMAS LEE , ROCHESTER MINN , MAGRISSO ISRAEL BEN , SLACK KEITH KENNETH , SMITH RICHARD STANTON
Abstract: Data transfers between input/output (I/O) devices and a central processing unit (CPU) take place under instruction or base cycle steal control a byte at a time where the I/O device attachments connect to ports and the ports connect to the CPU. Data transfer can be synchronous or asynchronous. The port involved in the data transfer sends out a device address and command information simultaneously on port data bus out and command bus out, respectively, to the I/O attachments. The addressed I/O device can respond any time within a predetermined time interval. If an I/O device does not respond within the time interval, a blast condition generated by the port causes the I/O attachments to clear the busses between it and the port. During execution of an I/O instruction, the CPU clock is first held in a particular time state while phase clocks and port clocks continue to run and synchronization between the port and I/O attachment is taking place. Upon completion of the synchronization sequence, the port generates an advance time signal to the CPU to advance the CPU clock. The CPU clock runs and the storage clock can be activated depending upon the type of I/O instruction being executed, the CPU clock runs until it reaches a second particular time state and then remains at that particular time state until the port again generates an advance time signal to the CPU. The activity taking place as the CPU clock is advancing depends upon the type of I/O instruction, but generally a data transfer occurs, and the data is entered into or transferred from local storage registers or main or control storage. The extended second particular time state is used for a de-synchronization sequence between the port and I/O attachment.
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