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    Post-decoding error check with diagnostics for product codes
    2.
    发明专利
    Post-decoding error check with diagnostics for product codes 未知

    公开(公告)号：GB2562352A

    公开(公告)日：2018-11-14

    申请号：GB201803554

    申请日：2016-11-29

    Applicant: IBM

    Inventor： ROBERT ALLEN HUTCHINS ,  STEVEN ROSS BENTLEY ,  KEISUKE TANAKA ,  ROY DARON CIDECIYAN

    IPC: H03M13/29 ,  G11B20/18

    Abstract: A system includes a controller and logic integrated with and/or executable by the controller. The logic is configured to perform iterative decoding on encoded data to obtain decoded data. At least three decoding operations are performed in the iterative decoding, with the decoding operations being selected from a group comprising:C1 decoding and C2 decoding. The logic is also configured to perform post-decoding error diagnostics on a first portion of the decoded data in response to not obtaining a valid product codeword in the first portion after the iterative decoding of the encoded data. Other systems, methods, and computer program products for producing post-decoding error signatures are also presented.

    Priority-based decoding
    3.
    发明专利
    Priority-based decoding 未知

    公开(公告)号：GB2545964B

    公开(公告)日：2021-05-05

    申请号：GB201618530

    申请日：2016-11-03

    Applicant: IBM

    Inventor： KEISUKE TANAKA ,  STEVEN ROSS BENTLEY ,  SIMEON FURRER ,  ROY DARON CIDECIYAN

    IPC: G11B20/18

    Abstract: In one embodiment, a tape drive includes a magnetic head having a plurality of read sensors, each read sensor being configured to read data simultaneously. The tape drive also includes a controller and logic integrated with and/or executable by the controller. The logic is configured to receive encoded data read from a plurality of tracks of a magnetic tape medium simultaneously. The logic is also configured to perform priority-based decoding on the encoded data based on erasure coefficients associated with at least one codeword of the encoded data. In another embodiment, a controller-implemented method includes receiving encoded data read from a plurality of tracks of a magnetic tape medium simultaneously and performing priority-based decoding on the encoded data based on erasure coefficients associated with at least one codeword of the encoded data.

    Solid-state storage system with parallel access of multiple flash/pcm devices
    4.
    发明专利
    Solid-state storage system with parallel access of multiple flash/pcm devices 未知

    公开(公告)号：GB2488057B

    公开(公告)日：2017-12-06

    申请号：GB201207470

    申请日：2010-11-26

    Applicant: IBM

    Inventor： THEODORE A ANTONAKOPOULOS ,  ROY DARON CIDECIYAN ,  EVANGELOS S ELEFTHERIOU ,  ROBERT HAAS ,  XIAO-YU HU ,  ILIAS ILIADIS

    IPC: G06F11/10 ,  G11C29/00

    Abstract: Systems and methods are provided that confront the problem of failed storage integrated circuits (ICs) in a solid state drive (SSD) by using a fault-tolerant architecture along with one error correction code (ECC) mechanism for random/burst error corrections and an L-fold interleaving mechanism. The systems and methods described herein keep the SSD operational when one or more integrated circuits fail and allow the recovery of previously stored data from failed integrated circuits and allow random/burst errors to be corrected in other operational integrated circuits. These systems and methods replace the failed integrated circuits with fully functional/operational integrated circuits treated herein as spare integrated circuits. Furthermore, these systems and methods improve I/O performance in terms of maximum achievable read/write data rate.

    Priority-based decoding
    5.
    发明专利
    Priority-based decoding 未知

    公开(公告)号：GB2545964A

    公开(公告)日：2017-07-05

    申请号：GB201618530

    申请日：2016-11-03

    Applicant: IBM

    Inventor： KEISUKE TANAKA ,  STEVEN ROSS BENTLEY ,  SIMEON FURRER ,  ROY DARON CIDECIYAN

    IPC: G11B20/18

    Abstract: A tape drive includes a magnetic head having a plurality K of read sensors, each read sensor being configured to read data simultaneously. The tape drive also includes a controller and logic integrated with and/or executable by the controller. The logic is configured to receive encoded data read from a plurality of tracks of a magnetic tape medium simultaneously. The logic is also configured to perform priority-based decoding on the encoded data based on erasure coefficients associated with at least one codeword of the encoded data. Erasure pointers for C2 decoding may be enabled if, and only if, C1 codewords include a large number of byte errors. Each erasure pointer may have an erasure coefficient (wi fig. 6) indicating probability that the C2 decoder should treat the corresponding C1 bytes as erasures.

    Low latency lateral decoding of data for retrieval from magnetic tape
    7.
    发明专利
    Low latency lateral decoding of data for retrieval from magnetic tape 未知

    公开(公告)号：GB2558416B

    公开(公告)日：2019-02-27

    申请号：GB201720581

    申请日：2017-12-11

    Applicant: IBM

    Inventor： ROY DARON CIDECIYAN ,  SIMEON FURRER ,  ERNEST STEWART GALE ,  MARK ALFRED LANTZ

    IPC: G11B27/36 ,  G11B20/18

    Abstract: In one embodiment, a method includes reading a plurality of narrow-spread (NS) codewords from M tracks of a magnetic tape medium using a plurality of read elements, the plurality of NS codewords collectively comprising data logically organized as a predetermined number of two-dimensional arrays. Each two-dimensional array includes a predetermined number of NS codewords positioned orthogonally to a predetermined number of wide-spread (WS) codewords, with a first NS codeword from a first two-dimensional array being read in its entirety from the magnetic tape medium prior to reading a second NS codeword from the first two-dimensional array. The method also includes laterally decoding each NS codeword from the first two-dimensional array read from the M tracks of the magnetic tape medium in succession prior to decoding any WS codewords from the first two-dimensional array. The NS codewords are protected with a stronger encoding than the WS codewords within each two-dimensional array.

    Low latency lateral decoding of data for retrieval from magnetic tape
    8.
    发明专利
    Low latency lateral decoding of data for retrieval from magnetic tape 未知

    公开(公告)号：GB2558416A

    公开(公告)日：2018-07-11

    申请号：GB201720581

    申请日：2017-12-11

    Applicant: IBM

    Inventor： ROY DARON CIDECIYAN ,  SIMEON FURRER ,  ERNEST STEWART GALE ,  MARK ALFRED LANTZ

    IPC: G11B27/36 ,  G11B20/18

    Abstract: A method includes reading a plurality of narrow-spread (NS) codewords 812 from M tracks of a magnetic tape medium 802 using a plurality of read elements, the plurality of NS codewords collectively comprising data logically organized as a predetermined number of two-dimensional arrays. Each two-dimensional array includes a predetermined number of NS codewords positioned orthogonally to a predetermined number of wide-spread (WS) codewords 810, with a first NS codeword from a first two-dimensional array 804 being read in its entirety from the magnetic tape medium prior to reading a second NS codeword from the first two-dimensional array. The method also includes laterally decoding each NS codeword from the first two-dimensional array read from the M tracks of the magnetic tape medium in succession prior to decoding any WS codewords from the first two-dimensional array. The NS codewords are protected with a stronger encoding than the WS codewords within each two-dimensional array. The lower latency from decoding the NS codewords can be used to drive decision-directed digital front-end functions of read channels such as asymmetry cancellation, adaptive equalization, interpolation and gain adjustment.

    Intra-block memory wear leveling
    9.
    发明专利
    Intra-block memory wear leveling 未知

    公开(公告)号：GB2509478B

    公开(公告)日：2016-08-17

    申请号：GB201205097

    申请日：2010-11-29

    Applicant: IBM

    Inventor： THEODOROS A ANTONAKOPOULOS ,  ROY DARON CIDECIYAN ,  XIAO-YU HU ,  ILIAS ILIADIS ,  ROMAN A PLETKA

    IPC: G06F12/02 ,  G06F3/06

    Abstract: A method for intra-block wear leveling within solid-state memory subjected to wear, having a plurality of memory cells includes the step of writing to at least certain ones of the plurality of memory cells, in a non-uniform manner, such as to balance the wear of the at least certain ones of the plurality of memory cells within the solid-state memory, at intra-block level. For example, if a behavior of at least some of the plurality of memory cells is not characterized, then the method may comprise characterizing a behavior of at least some of the plurality of memory cells and writing to at least certain ones of the plurality of memory cells, based on the characterized behavior, and in a non-uniform manner.

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